# HG changeset patch # User Paul Boddie # Date 1433877040 -7200 # Node ID 83787736d5c2ff18771cf8e8b1b5389bc865a1d9 # Parent 06e6b276d694f1a77d3bc214ee2569fab3f5157f Separated board-specific functionality out from common functionality in an attempt to introduce tentative jz4730 and MiniPC support. diff -r 06e6b276d694 -r 83787736d5c2 include/nanonote.h --- a/include/nanonote.h Tue Jun 09 00:03:27 2015 +0200 +++ b/include/nanonote.h Tue Jun 09 21:10:40 2015 +0200 @@ -1,7 +1,7 @@ /* - * Copyright (C) 2015 Paul Boddie * Copyright (C) 2009 Qi Hardware Inc. * Authors: Xiangfu Liu + * Copyright (C) 2015 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -33,44 +33,6 @@ #define LCD_BPP LCD_COLOR32 /* - * RAM configuration - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* - * SDRAM configuration (timings in ns) - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define SDRAM_COL 9 /* Column address: 8 to 12 */ -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ -#define SDRAM_TRAS 45 /* RAS# Active Time */ -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define SDRAM_TPC 20 /* RAS# Precharge Time */ -#define SDRAM_TRWL 7 /* Write Latency Time */ -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ - -#define SDRAM_ROW0 11 /* Row address minimum */ -#define SDRAM_COL0 8 /* Column address minimum */ -#define SDRAM_BANK40 0 /* Bank minimum */ - -/* - * Cache configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * Memory configuration - */ -#define KSEG0 0x80000000 -#define PAGE_SIZE 4096 - -/* * GPIO definition * See: http://en.qi-hardware.com/wiki/Hardware_basics */ diff -r 06e6b276d694 -r 83787736d5c2 include/sdram.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/include/sdram.h Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,68 @@ +/* + * Common SDRAM configuration + * + * Copyright (C) 2009 Qi Hardware Inc. + * Authors: Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA + */ + +#ifndef __SDRAM_H__ +#define __SDRAM_H__ + +/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h + via u-boot/arch/mips/include/asm/io.h */ +/* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */ +#define virt_to_phys(n) ((int) n) + +/* + * RAM configuration + */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* + * SDRAM configuration (timings in ns) + */ +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ + +#define SDRAM_ROW0 11 /* Row address minimum */ +#define SDRAM_COL0 8 /* Column address minimum */ +#define SDRAM_BANK40 0 /* Bank minimum */ + +/* + * Cache configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * Memory configuration + */ +#define KSEG0 0x80000000 +#define PAGE_SIZE 4096 + +#endif /* __SDRAM_H__ */ diff -r 06e6b276d694 -r 83787736d5c2 stage1/board-nanonote.c --- a/stage1/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200 +++ b/stage1/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200 @@ -3,7 +3,7 @@ * * Copyright (C) 2015 Paul Boddie * Copyright (C) Xiangfu Liu - * Copyright (C) 2006 Ingenic Semiconductor, + * Copyright (C) 2005-2006 Ingenic Semiconductor, * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, * * This program is free software; you can redistribute it and/or modify it under @@ -21,7 +21,7 @@ */ #include "jz4740.h" -#include "nanonote.h" +#include "sdram.h" #include "usb_boot_defines.h" /* These arguments are initialised by usbboot and are defined in... @@ -82,16 +82,19 @@ (2 << CPM_CPCCR_MDIV_BIT) | (2 << CPM_CPCCR_LDIV_BIT); - /* Determine the divider clock output based on the PCS bit. */ - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - /* Init USB Host clock. - * Divisor == UHCCDR + 1 * Desired frequency == 48MHz */ +#ifdef CONFIG_CPU_JZ4730 + cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); +#else + /* Determine the divider clock output based on the PCS bit. */ + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); + + /* Divisor == UHCCDR + 1 */ REG_CPM_UHCCDR = pllout2 / 48000000 - 1; +#endif nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ @@ -172,10 +175,23 @@ EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + if (FW_SDRAM_BW16) + sdmode <<= 1; + else + sdmode <<= 2; +#endif + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ REG_EMC_DMCR = dmcr; REG8(EMC_SDMR0|sdmode) = 0; + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + REG8(EMC_SDMR1|sdmode) = 0; +#endif + /* Wait for precharge, > 200us */ tmp = (cpu_clk / 1000000) * 1000; while (tmp--); @@ -198,6 +214,11 @@ REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; REG8(EMC_SDMR0|sdmode) = 0; + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + REG8(EMC_SDMR1|sdmode) = 0; +#endif + /* Set back to basic DMCR value */ REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; diff -r 06e6b276d694 -r 83787736d5c2 stage2/Makefile --- a/stage2/Makefile Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/Makefile Tue Jun 09 21:10:40 2015 +0200 @@ -42,8 +42,8 @@ # Ordering of objects is important and cannot be left to replacement rules. -SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c -OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o +SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c jzlcd.c board.c +OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o jzlcd.o board.o .PHONY: all clean distclean diff -r 06e6b276d694 -r 83787736d5c2 stage2/board-nanonote.c --- a/stage2/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200 @@ -1,10 +1,10 @@ /* * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools. * - * Copyright (C) 2015 Paul Boddie + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * Copyright (C) 2006 Ingenic Semiconductor, * Copyright (C) Xiangfu Liu - * Copyright (C) 2006 Ingenic Semiconductor, - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * Copyright (C) 2015 Paul Boddie * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License as published by the Free Software @@ -20,7 +20,7 @@ * this program. If not, see . */ -#include "jz4740.h" +#include "board.h" #include "nanonote.h" /* Later initialisation functions. */ @@ -106,37 +106,10 @@ REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ } -unsigned long get_memory_size(void) -{ - unsigned int dmcr; - unsigned int rows, cols, dw, banks; - unsigned long size; - - dmcr = REG_EMC_DMCR; - rows = SDRAM_ROW0 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = SDRAM_COL0 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} - /* Timer routines. */ -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ -#define TIMER_HZ CONFIG_SYS_HZ - -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ - -static unsigned long timestamp; -static unsigned long lastdec; - -void reset_timer_masked(void); -unsigned long get_timer_masked(void); -void udelay_masked(unsigned long usec); +unsigned long timestamp; +unsigned long lastdec; /* * timer without interrupts @@ -158,176 +131,3 @@ return 0; } - -void reset_timer(void) -{ - reset_timer_masked (); -} - -unsigned long get_timer(unsigned long base) -{ - return get_timer_masked () - base; -} - -void set_timer(unsigned long t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - unsigned long tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } - else { - if (usec >= 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -unsigned long get_timer_masked (void) -{ - unsigned long now = READ_TIMER; - - if (lastdec <= now) { - /* normal mode */ - timestamp += (now - lastdec); - } else { - /* we have an overflow ... */ - timestamp += TIMER_FDATA + now - lastdec; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - unsigned long tmo; - unsigned long endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - unsigned long now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -unsigned long get_tbclk (void) -{ - return TIMER_HZ; -} - -/* CPU-specific routines from U-Boot. - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c - See: u-boot/arch/mips/include/asm/cacheops.h -*/ - -#define Index_Store_Tag_I 0x08 -#define Index_Writeback_Inv_D 0x15 - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Store_Tag_I), "r"(addr)); - } - - /* invalicate btb */ - asm volatile ( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Writeback_Inv_D), "r"(addr)); - } - - asm volatile ("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff -r 06e6b276d694 -r 83787736d5c2 stage2/board-nanonote.h --- a/stage2/board-nanonote.h Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/board-nanonote.h Tue Jun 09 21:10:40 2015 +0200 @@ -1,5 +1,5 @@ -#ifndef __BOARD_NANONOTE2_H__ -#define __BOARD_NANONOTE2_H__ +#ifndef __BOARD_NANONOTE_H__ +#define __BOARD_NANONOTE_H__ /* Initialisation functions. */ @@ -8,10 +8,4 @@ void rtc_init(void); int timer_init(void); -/* Utility functions. */ - -void udelay(unsigned long usec); -void flush_cache_all(void); -unsigned long get_memory_size(void); - -#endif /* __BOARD_NANONOTE2_H__ */ +#endif /* __BOARD_NANONOTE_H__ */ diff -r 06e6b276d694 -r 83787736d5c2 stage2/board.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/board.c Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,219 @@ +/* + * Common routines supporting board initialisation. + * + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * Copyright (C) 2005-2006 Ingenic Semiconductor, + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "sdram.h" +#include "board.h" + +unsigned long get_memory_size(void) +{ + unsigned int dmcr; + unsigned int rows, cols, dw, banks; + unsigned long size; + + dmcr = REG_EMC_DMCR; + rows = SDRAM_ROW0 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); + cols = SDRAM_COL0 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; + + size = (1 << (rows + cols)) * dw * banks; + + return size; +} + +/* Timer routines. */ + +extern unsigned long timestamp; +extern unsigned long lastdec; + +unsigned long get_timer_masked (void) +{ + unsigned long now = READ_TIMER; + + if (lastdec <= now) { + /* normal mode */ + timestamp += (now - lastdec); + } else { + /* we have an overflow ... */ + timestamp += TIMER_FDATA + now - lastdec; + } + lastdec = now; + + return timestamp; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked (); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked () - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + unsigned long tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } + else { + if (usec >= 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void udelay_masked (unsigned long usec) +{ + unsigned long tmo; + unsigned long endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + unsigned long now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +unsigned long get_tbclk (void) +{ + return TIMER_HZ; +} + +/* CPU-specific routines from U-Boot. + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c + See: u-boot/arch/mips/include/asm/cacheops.h +*/ + +#define Index_Store_Tag_I 0x08 +#define Index_Writeback_Inv_D 0x15 + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Store_Tag_I), "r"(addr)); + } + + /* invalicate btb */ + asm volatile ( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Writeback_Inv_D), "r"(addr)); + } + + asm volatile ("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} diff -r 06e6b276d694 -r 83787736d5c2 stage2/board.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/board.h Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,23 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +/* Utility functions. */ + +void udelay(unsigned long usec); +void flush_cache_all(void); +unsigned long get_memory_size(void); + +#ifdef CONFIG_CPU_JZ4730 +#include "jz4730.h" +#define READ_TIMER __ost_get_count(TIMER_CHAN) /* macro to read the 32 bit timer */ +#define TIMER_FDATA 0xffffffff /* timer full data value */ +#else +#include "jz4740.h" +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ +#define TIMER_FDATA 0xffff /* timer full data value */ +#endif + +#define TIMER_HZ CONFIG_SYS_HZ +#define TIMER_CHAN 0 + +#endif /* __BOARD_H__ */ diff -r 06e6b276d694 -r 83787736d5c2 stage2/jzlcd.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/jzlcd.c Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,389 @@ +/* + * JzRISC lcd controller + * + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "nanonote_gpm940b0.h" +#include "sdram.h" +#include "jzlcd.h" +#include "board.h" + +#define align2(n) (n)=((((n)+1)>>1)<<1) +#define align4(n) (n)=((((n)+3)>>2)<<2) +#define align8(n) (n)=((((n)+7)>>3)<<3) + +extern struct jzfb_info jzfb; + +unsigned long lcd_get_size(void) +{ + int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + return line_length * panel_info.vl_row; +} + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); +static void jz_lcd_desc_init(vidinfo_t *vid); +static int jz_lcd_hw_init(vidinfo_t *vid); + +void lcd_ctrl_init (void *lcdbase) +{ + jz_lcd_init_mem(lcdbase, &panel_info); + jz_lcd_desc_init(&panel_info); + jz_lcd_hw_init(&panel_info); +} + +/* + * Before enabled lcd controller, lcd registers should be configured correctly. + */ +void lcd_enable (void) +{ + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ +} + +void lcd_disable (void) +{ + REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ + /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ +} + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) +{ + unsigned long palette_mem_size; + struct jz_fb_info *fbi = &vid->jz_fb; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (unsigned long)lcdbase; + fbi->palette_size = 256; + palette_mem_size = fbi->palette_size * sizeof(u16); + + /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ + /* locate palette and descs at end of page following fb */ + fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} + +static void jz_lcd_desc_init(vidinfo_t *vid) +{ + struct jz_fb_info * fbi; + fbi = &vid->jz_fb; + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; + + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ + + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); + + if(NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); + } else { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ + } + + flush_cache_all(); +} + +static int jz_lcd_hw_init(vidinfo_t *vid) +{ + struct jz_fb_info *fbi = &vid->jz_fb; + unsigned int val = 0; + unsigned int pclk; + unsigned int stnH; + int pll_div; + + /* Setting Control register */ + switch (jzfb.bpp) { + case 1: + val |= LCD_CTRL_BPP_1; + break; + case 2: + val |= LCD_CTRL_BPP_2; + break; + case 4: + val |= LCD_CTRL_BPP_4; + break; + case 8: + val |= LCD_CTRL_BPP_8; + break; + case 15: + val |= LCD_CTRL_RGB555; + case 16: + val |= LCD_CTRL_BPP_16; + break; + case 17 ... 32: + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ + break; + + default: + /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ + val |= LCD_CTRL_BPP_16; + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.bpp) { + case 1: + /* val |= LCD_CTRL_PEDN; */ + case 2: + val |= LCD_CTRL_FRC_2; + break; + case 4: + val |= LCD_CTRL_FRC_4; + break; + case 8: + default: + val |= LCD_CTRL_FRC_16; + break; + } + break; + } + + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.cfg & STN_DAT_PINMASK) { + case STN_DAT_PIN1: + /* Do not adjust the hori-param value. */ + break; + case STN_DAT_PIN2: + align2(jzfb.hsw); + align2(jzfb.elw); + align2(jzfb.blw); + break; + case STN_DAT_PIN4: + align4(jzfb.hsw); + align4(jzfb.elw); + align4(jzfb.blw); + break; + case STN_DAT_PIN8: + align8(jzfb.hsw); + align8(jzfb.elw); + align8(jzfb.blw); + break; + } + break; + } + + REG_LCD_CTRL = val; + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + stnH = jzfb.h >> 1; + else + stnH = jzfb.h; + + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); + + /* Screen setting */ + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); + REG_LCD_DAV = (0 << 16) | (stnH); + + /* AC BIAs signal */ + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); + + break; + + case MODE_TFT_GEN: + case MODE_TFT_SHARP: + case MODE_TFT_CASIO: + case MODE_TFT_SAMSUNG: + case MODE_8BIT_SERIAL_TFT: + case MODE_TFT_18BIT: + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_TFT_SAMSUNG: + { + unsigned int total, tp_s, tp_e, ckv_s, ckv_e; + unsigned int rev_s, rev_e, inv_s, inv_e; + + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + tp_s = jzfb.blw + jzfb.w + 1; + tp_e = tp_s + 1; + /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ + ckv_s = tp_s - pclk/(1000000000/4100); + ckv_e = tp_s + total; + rev_s = tp_s - 11; /* -11.5 clk */ + rev_e = rev_s + total; + inv_s = tp_s; + inv_e = inv_s + total; + REG_LCD_CLS = (tp_s << 16) | tp_e; + REG_LCD_PS = (ckv_s << 16) | ckv_e; + REG_LCD_SPL = (rev_s << 16) | rev_e; + REG_LCD_REV = (inv_s << 16) | inv_e; + jzfb.cfg |= STFT_REVHI | STFT_SPLHI; + break; + } + case MODE_TFT_SHARP: + { + unsigned int total, cls_s, cls_e, ps_s, ps_e; + unsigned int spl_s, spl_e, rev_s, rev_e; + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + spl_s = 1; + spl_e = spl_s + 1; + cls_s = 0; + cls_e = total - 60; /* > 4us (pclk = 80ns) */ + ps_s = cls_s; + ps_e = cls_e; + rev_s = total - 40; /* > 3us (pclk = 80ns) */ + rev_e = rev_s + total; + jzfb.cfg |= STFT_PSHI; + REG_LCD_SPL = (spl_s << 16) | spl_e; + REG_LCD_CLS = (cls_s << 16) | cls_e; + REG_LCD_PS = (ps_s << 16) | ps_e; + REG_LCD_REV = (rev_s << 16) | rev_e; + break; + } + case MODE_TFT_CASIO: + break; + } + + /* Configure the LCD panel */ + REG_LCD_CFG = jzfb.cfg; + + /* Timing setting */ + __cpm_stop_lcd(); + + val = jzfb.fclk; /* frame clk */ + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } else { + /* serial mode: Hsync period = 3*Width_Pixel */ + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + pclk = (pclk * 3); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk >>= 1; + +#ifdef CONFIG_CPU_JZ4730 + val = __cpm_get_pllout() / pclk; + REG_CPM_CFCR2 = val - 1; + val = pclk * 4 ; + if ( val > 150000000 ) { + val = 150000000; + } + val = __cpm_get_pllout() / val; + val--; + if ( val > 0xF ) + val = 0xF; + __cpm_set_lcdclk_div(val); + REG_CPM_CFCR |= CPM_CFCR_UPE; +#else + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ + pll_div = pll_div ? 1 : 2 ; + val = ( __cpm_get_pllout()/pll_div ) / pclk; + val--; + if ( val > 0x1ff ) { + val = 0x1ff; + } + __cpm_set_pixdiv(val); + + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ + if ( val > 150000000 ) { + val = 150000000; + } + val = ( __cpm_get_pllout()/pll_div ) / val; + val--; + if ( val > 0x1f ) { + val = 0x1f; + } + __cpm_set_ldiv( val ); + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ +#endif + __cpm_start_lcd(); + udelay(1000); + + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ + + return 0; +} + +void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) +{ +} + +void lcd_initcolregs (void) +{ +} diff -r 06e6b276d694 -r 83787736d5c2 stage2/jzlcd.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/jzlcd.h Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,103 @@ +/* + * JzRISC lcd controller + * + * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __JZLCD_H__ +#define __JZLCD_H__ + +unsigned long lcd_get_size(void); +void lcd_ctrl_init(void *lcdbase); +void lcd_enable(void); +void lcd_disable(void); + +struct lcd_desc{ + unsigned int next_desc; /* LCDDAx */ + unsigned int databuf; /* LCDSAx */ + unsigned int frame_id; /* LCDFIDx */ + unsigned int cmd; /* LCDCMDx */ +}; + +struct jzfb_info { + unsigned int cfg; /* panel mode and pin usage etc. */ + unsigned int w; + unsigned int h; + unsigned int bpp; /* bit per pixel */ + unsigned int fclk; /* frame clk */ + unsigned int hsw; /* hsync width, in pclk */ + unsigned int vsw; /* vsync width, in line count */ + unsigned int elw; /* end of line, in pclk */ + unsigned int blw; /* begin of line, in pclk */ + unsigned int efw; /* end of frame, in line count */ + unsigned int bfw; /* begin of frame, in line count */ +}; + +#define MODE_MASK 0x0f +#define MODE_TFT_GEN 0x00 +#define MODE_TFT_SHARP 0x01 +#define MODE_TFT_CASIO 0x02 +#define MODE_TFT_SAMSUNG 0x03 +#define MODE_CCIR656_NONINT 0x04 +#define MODE_CCIR656_INT 0x05 +#define MODE_STN_COLOR_SINGLE 0x08 +#define MODE_STN_MONO_SINGLE 0x09 +#define MODE_STN_COLOR_DUAL 0x0a +#define MODE_STN_MONO_DUAL 0x0b +#define MODE_8BIT_SERIAL_TFT 0x0c + +#define MODE_TFT_18BIT (1<<7) + +#define STN_DAT_PIN1 (0x00 << 4) +#define STN_DAT_PIN2 (0x01 << 4) +#define STN_DAT_PIN4 (0x02 << 4) +#define STN_DAT_PIN8 (0x03 << 4) +#define STN_DAT_PINMASK STN_DAT_PIN8 + +#define STFT_PSHI (1 << 15) +#define STFT_CLSHI (1 << 14) +#define STFT_SPLHI (1 << 13) +#define STFT_REVHI (1 << 12) + +#define SYNC_MASTER (0 << 16) +#define SYNC_SLAVE (1 << 16) + +#define DE_P (0 << 9) +#define DE_N (1 << 9) + +#define PCLK_P (0 << 10) +#define PCLK_N (1 << 10) + +#define HSYNC_P (0 << 11) +#define HSYNC_N (1 << 11) + +#define VSYNC_P (0 << 8) +#define VSYNC_N (1 << 8) + +#define DATA_NORMAL (0 << 17) +#define DATA_INVERSE (1 << 17) + + +/* Jz LCDFB supported I/O controls. */ +#define FBIOSETBACKLIGHT 0x4688 +#define FBIODISPON 0x4689 +#define FBIODISPOFF 0x468a +#define FBIORESET 0x468b +#define FBIOPRINT_REG 0x468c + +#endif /* __JZLCD_H__ */ diff -r 06e6b276d694 -r 83787736d5c2 stage2/lcd.c --- a/stage2/lcd.c Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/lcd.c Tue Jun 09 21:10:40 2015 +0200 @@ -1,8 +1,8 @@ /* * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools. * + * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, * Copyright (C) 2015 Paul Boddie - * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License as published by the Free Software @@ -20,7 +20,9 @@ #include "xburst_types.h" #include "nanonote_gpm940b0.h" -#include "board-nanonote.h" +#include "jzlcd.h" +#include "sdram.h" +#include "board.h" #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) diff -r 06e6b276d694 -r 83787736d5c2 stage2/minipc_claa070vc01.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/minipc_claa070vc01.c Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,33 @@ +/* + * Minibook screen details + * + * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "minipc_claa070vc01.h" +#include "jzlcd.h" + +struct jzfb_info jzfb = { + MODE_GENERIC_TFT | PCLK_N | HSYNC_N | VSYNC_N, + 800, 480, 16, 60, 80, 20, 0, 0, 0, 0 +}; + +vidinfo_t panel_info = { + 800, 480, LCD_BPP, +}; diff -r 06e6b276d694 -r 83787736d5c2 stage2/minipc_claa070vc01.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/minipc_claa070vc01.h Tue Jun 09 21:10:40 2015 +0200 @@ -0,0 +1,26 @@ +/* + * Minibook panel-specific definitions + * + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MINIPC_CLAA070VC01_H__ +#define __MINIPC_CLAA070VC01_H__ + +#endif /* __MINIPC_CLAA070VC01_H__ */ diff -r 06e6b276d694 -r 83787736d5c2 stage2/nanonote_gpm940b0.c --- a/stage2/nanonote_gpm940b0.c Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/nanonote_gpm940b0.c Tue Jun 09 21:10:40 2015 +0200 @@ -1,5 +1,5 @@ /* - * JzRISC lcd controller + * Ben NanoNote screen details * * Copyright (C) Xiangfu Liu * Copyright (C) 2015 Paul Boddie @@ -20,33 +20,10 @@ * MA 02111-1307 USA */ -/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h - via u-boot/arch/mips/include/asm/io.h */ -/* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */ -#define virt_to_phys(n) ((int) n) - #include "nanonote_gpm940b0.h" -#include "board-nanonote.h" - -#define align2(n) (n)=((((n)+1)>>1)<<1) -#define align4(n) (n)=((((n)+3)>>2)<<2) -#define align8(n) (n)=((((n)+7)>>3)<<3) +#include "jzlcd.h" -struct jzfb_info { - unsigned int cfg; /* panel mode and pin usage etc. */ - unsigned int w; - unsigned int h; - unsigned int bpp; /* bit per pixel */ - unsigned int fclk; /* frame clk */ - unsigned int hsw; /* hsync width, in pclk */ - unsigned int vsw; /* vsync width, in line count */ - unsigned int elw; /* end of line, in pclk */ - unsigned int blw; /* begin of line, in pclk */ - unsigned int efw; /* end of frame, in line count */ - unsigned int bfw; /* begin of frame, in line count */ -}; - -static struct jzfb_info jzfb = { +struct jzfb_info jzfb = { MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 }; @@ -54,350 +31,3 @@ vidinfo_t panel_info = { 320, 240, LCD_BPP, }; - -unsigned long lcd_get_size(void) -{ - int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; - return line_length * panel_info.vl_row; -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); -static void jz_lcd_desc_init(vidinfo_t *vid); -static int jz_lcd_hw_init(vidinfo_t *vid); - -void lcd_ctrl_init (void *lcdbase) -{ - jz_lcd_init_mem(lcdbase, &panel_info); - jz_lcd_desc_init(&panel_info); - jz_lcd_hw_init(&panel_info); -} - -/* - * Before enabled lcd controller, lcd registers should be configured correctly. - */ -void lcd_enable (void) -{ - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -} - -void lcd_disable (void) -{ - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) -{ - unsigned long palette_mem_size; - struct jz_fb_info *fbi = &vid->jz_fb; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (unsigned long)lcdbase; - fbi->palette_size = 256; - palette_mem_size = fbi->palette_size * sizeof(u16); - - /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ - /* locate palette and descs at end of page following fb */ - fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} - -static void jz_lcd_desc_init(vidinfo_t *vid) -{ - struct jz_fb_info * fbi; - fbi = &vid->jz_fb; - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; - - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ - - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); - - if(NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); - } else { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ - } - - flush_cache_all(); -} - -static int jz_lcd_hw_init(vidinfo_t *vid) -{ - struct jz_fb_info *fbi = &vid->jz_fb; - unsigned int val = 0; - unsigned int pclk; - unsigned int stnH; - int pll_div; - - /* Setting Control register */ - switch (jzfb.bpp) { - case 1: - val |= LCD_CTRL_BPP_1; - break; - case 2: - val |= LCD_CTRL_BPP_2; - break; - case 4: - val |= LCD_CTRL_BPP_4; - break; - case 8: - val |= LCD_CTRL_BPP_8; - break; - case 15: - val |= LCD_CTRL_RGB555; - case 16: - val |= LCD_CTRL_BPP_16; - break; - case 17 ... 32: - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ - break; - - default: - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ - val |= LCD_CTRL_BPP_16; - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.bpp) { - case 1: - /* val |= LCD_CTRL_PEDN; */ - case 2: - val |= LCD_CTRL_FRC_2; - break; - case 4: - val |= LCD_CTRL_FRC_4; - break; - case 8: - default: - val |= LCD_CTRL_FRC_16; - break; - } - break; - } - - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.cfg & STN_DAT_PINMASK) { - case STN_DAT_PIN1: - /* Do not adjust the hori-param value. */ - break; - case STN_DAT_PIN2: - align2(jzfb.hsw); - align2(jzfb.elw); - align2(jzfb.blw); - break; - case STN_DAT_PIN4: - align4(jzfb.hsw); - align4(jzfb.elw); - align4(jzfb.blw); - break; - case STN_DAT_PIN8: - align8(jzfb.hsw); - align8(jzfb.elw); - align8(jzfb.blw); - break; - } - break; - } - - REG_LCD_CTRL = val; - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - stnH = jzfb.h >> 1; - else - stnH = jzfb.h; - - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); - - /* Screen setting */ - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); - REG_LCD_DAV = (0 << 16) | (stnH); - - /* AC BIAs signal */ - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); - - break; - - case MODE_TFT_GEN: - case MODE_TFT_SHARP: - case MODE_TFT_CASIO: - case MODE_TFT_SAMSUNG: - case MODE_8BIT_SERIAL_TFT: - case MODE_TFT_18BIT: - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_TFT_SAMSUNG: - { - unsigned int total, tp_s, tp_e, ckv_s, ckv_e; - unsigned int rev_s, rev_e, inv_s, inv_e; - - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - tp_s = jzfb.blw + jzfb.w + 1; - tp_e = tp_s + 1; - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ - ckv_s = tp_s - pclk/(1000000000/4100); - ckv_e = tp_s + total; - rev_s = tp_s - 11; /* -11.5 clk */ - rev_e = rev_s + total; - inv_s = tp_s; - inv_e = inv_s + total; - REG_LCD_CLS = (tp_s << 16) | tp_e; - REG_LCD_PS = (ckv_s << 16) | ckv_e; - REG_LCD_SPL = (rev_s << 16) | rev_e; - REG_LCD_REV = (inv_s << 16) | inv_e; - jzfb.cfg |= STFT_REVHI | STFT_SPLHI; - break; - } - case MODE_TFT_SHARP: - { - unsigned int total, cls_s, cls_e, ps_s, ps_e; - unsigned int spl_s, spl_e, rev_s, rev_e; - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - spl_s = 1; - spl_e = spl_s + 1; - cls_s = 0; - cls_e = total - 60; /* > 4us (pclk = 80ns) */ - ps_s = cls_s; - ps_e = cls_e; - rev_s = total - 40; /* > 3us (pclk = 80ns) */ - rev_e = rev_s + total; - jzfb.cfg |= STFT_PSHI; - REG_LCD_SPL = (spl_s << 16) | spl_e; - REG_LCD_CLS = (cls_s << 16) | cls_e; - REG_LCD_PS = (ps_s << 16) | ps_e; - REG_LCD_REV = (rev_s << 16) | rev_e; - break; - } - case MODE_TFT_CASIO: - break; - } - - /* Configure the LCD panel */ - REG_LCD_CFG = jzfb.cfg; - - /* Timing setting */ - __cpm_stop_lcd(); - - val = jzfb.fclk; /* frame clk */ - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } else { - /* serial mode: Hsync period = 3*Width_Pixel */ - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - pclk = (pclk * 3); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk >>= 1; - - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ - pll_div = pll_div ? 1 : 2 ; - val = ( __cpm_get_pllout()/pll_div ) / pclk; - val--; - if ( val > 0x1ff ) { - /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ - val = 0x1ff; - } - __cpm_set_pixdiv(val); - - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ - if ( val > 150000000 ) { - /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ - /* printf("Change LCDClock to 150MHz\n"); */ - val = 150000000; - } - val = ( __cpm_get_pllout()/pll_div ) / val; - val--; - if ( val > 0x1f ) { - /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ - val = 0x1f; - } - __cpm_set_ldiv( val ); - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ - - __cpm_start_lcd(); - udelay(1000); - - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ - - return 0; -} - -void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) -{ -} - -void lcd_initcolregs (void) -{ -} diff -r 06e6b276d694 -r 83787736d5c2 stage2/nanonote_gpm940b0.h --- a/stage2/nanonote_gpm940b0.h Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/nanonote_gpm940b0.h Tue Jun 09 21:10:40 2015 +0200 @@ -1,7 +1,8 @@ /* - * JzRISC lcd controller + * Ben NanoNote panel-specific definitions * - * Xiangfu Liu + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,75 +26,6 @@ #include "nanonote.h" #include "jz4740.h" -unsigned long lcd_get_size(void); -void lcd_ctrl_init(void *lcdbase); -void lcd_enable(void); -void lcd_disable(void); - -struct lcd_desc{ - unsigned int next_desc; /* LCDDAx */ - unsigned int databuf; /* LCDSAx */ - unsigned int frame_id; /* LCDFIDx */ - unsigned int cmd; /* LCDCMDx */ -}; - -#define MODE_MASK 0x0f -#define MODE_TFT_GEN 0x00 -#define MODE_TFT_SHARP 0x01 -#define MODE_TFT_CASIO 0x02 -#define MODE_TFT_SAMSUNG 0x03 -#define MODE_CCIR656_NONINT 0x04 -#define MODE_CCIR656_INT 0x05 -#define MODE_STN_COLOR_SINGLE 0x08 -#define MODE_STN_MONO_SINGLE 0x09 -#define MODE_STN_COLOR_DUAL 0x0a -#define MODE_STN_MONO_DUAL 0x0b -#define MODE_8BIT_SERIAL_TFT 0x0c - -#define MODE_TFT_18BIT (1<<7) - -#define STN_DAT_PIN1 (0x00 << 4) -#define STN_DAT_PIN2 (0x01 << 4) -#define STN_DAT_PIN4 (0x02 << 4) -#define STN_DAT_PIN8 (0x03 << 4) -#define STN_DAT_PINMASK STN_DAT_PIN8 - -#define STFT_PSHI (1 << 15) -#define STFT_CLSHI (1 << 14) -#define STFT_SPLHI (1 << 13) -#define STFT_REVHI (1 << 12) - -#define SYNC_MASTER (0 << 16) -#define SYNC_SLAVE (1 << 16) - -#define DE_P (0 << 9) -#define DE_N (1 << 9) - -#define PCLK_P (0 << 10) -#define PCLK_N (1 << 10) - -#define HSYNC_P (0 << 11) -#define HSYNC_N (1 << 11) - -#define VSYNC_P (0 << 8) -#define VSYNC_N (1 << 8) - -#define DATA_NORMAL (0 << 17) -#define DATA_INVERSE (1 << 17) - - -/* Jz LCDFB supported I/O controls. */ -#define FBIOSETBACKLIGHT 0x4688 -#define FBIODISPON 0x4689 -#define FBIODISPOFF 0x468a -#define FBIORESET 0x468b -#define FBIOPRINT_REG 0x468c - -/* - * LCD panel specific definition - */ -#define MODE (0xc9) /* 8bit serial RGB */ - #define __spi_write_reg1(reg, val) \ do { \ unsigned char no; \ diff -r 06e6b276d694 -r 83787736d5c2 stage2/stage2.c --- a/stage2/stage2.c Tue Jun 09 00:03:27 2015 +0200 +++ b/stage2/stage2.c Tue Jun 09 21:10:40 2015 +0200 @@ -1,8 +1,8 @@ /* * Ben NanoNote stage 2 payload test. * + * Copyright (C) Wolfgang Spraul * Copyright (C) 2015 Paul Boddie - * Copyright (C) Wolfgang Spraul * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License as published by the Free Software