# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1435685936 -7200
# Node ID 9f1c1c6e2ba831df4b6a17a57c154ced180a5f88
# Parent  17e853645d5d2133e959caecbb39c454c54c4ca5
Added more compatibility macros to slightly reduce separate code regions.

diff -r 17e853645d5d -r 9f1c1c6e2ba8 include/jz4730_compat.h
--- a/include/jz4730_compat.h	Tue Jun 30 16:10:40 2015 +0200
+++ b/include/jz4730_compat.h	Tue Jun 30 19:38:56 2015 +0200
@@ -23,6 +23,7 @@
 #define REG_CPM_CPCCR		REG_CPM_CFCR
 #define REG_CPM_CPPCR		REG_CPM_PLCR1
 
+#define CPM_CPCCR_CE		CPM_CFCR_UPE
 #define CPM_CPCCR_CDIV_BIT	CPM_CFCR_IFR_BIT
 #define CPM_CPCCR_HDIV_BIT	CPM_CFCR_SFR_BIT
 #define CPM_CPCCR_PDIV_BIT	CPM_CFCR_PFR_BIT
@@ -35,4 +36,6 @@
 #define CPM_CPPCR_PLLST_BIT	CPM_PLCR1_PLL1ST_BIT
 #define CPM_CPPCR_PLLEN		CPM_PLCR1_PLL1EN
 
+#define __cpm_set_ldiv		__cpm_set_lcdclk_div
+
 #endif /* __JZ4730_COMPAT_H__ */
diff -r 17e853645d5d -r 9f1c1c6e2ba8 stage2/jzlcd.c
--- a/stage2/jzlcd.c	Tue Jun 30 16:10:40 2015 +0200
+++ b/stage2/jzlcd.c	Tue Jun 30 19:38:56 2015 +0200
@@ -369,8 +369,6 @@
         val--;
         if ( val > 0xF )
                 val = 0xF;
-        __cpm_set_lcdclk_div(val);
-        REG_CPM_CFCR |= CPM_CFCR_UPE;
 #else
 	pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
 	pll_div = pll_div ? 1 : 2 ;
@@ -390,9 +388,10 @@
 	if ( val > 0x1f ) {
 		val = 0x1f;
 	}
+#endif
 	__cpm_set_ldiv( val );
 	REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
-#endif
+
 	__cpm_start_lcd();
 	udelay(1000);