# HG changeset patch # User Paul Boddie # Date 1433878600 -7200 # Node ID a63d68f0b926a355529a96dbe065f347f61c249a # Parent 25ad44524ef534c84d8b90cce3dddb858b903c01 Renamed stage 1 source files and extended tentative jz4730 support. diff -r 25ad44524ef5 -r a63d68f0b926 stage1/Makefile --- a/stage1/Makefile Tue Jun 09 21:26:39 2015 +0200 +++ b/stage1/Makefile Tue Jun 09 21:36:40 2015 +0200 @@ -42,8 +42,8 @@ # Ordering of objects is important and cannot be left to replacement rules. -SRC = head1.S stage1.c board-nanonote.c -OBJ = head1.o stage1.o board-nanonote.o +SRC = head1.S stage1.c board.c +OBJ = head1.o stage1.o board.o .PHONY: all clean distclean diff -r 25ad44524ef5 -r a63d68f0b926 stage1/board-nanonote.c --- a/stage1/board-nanonote.c Tue Jun 09 21:26:39 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,226 +0,0 @@ -/* - * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) Xiangfu Liu - * Copyright (C) 2005-2006 Ingenic Semiconductor, - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "jz4740.h" -#include "sdram.h" -#include "usb_boot_defines.h" - -/* These arguments are initialised by usbboot and are defined in... - /etc/xburst-tools/usbboot.cfg. */ - -struct fw_args *fw_args; -volatile u32 FW_CPU_ID; -volatile u8 FW_SDRAM_BW16; -volatile u8 FW_SDRAM_BANK4; -volatile u8 FW_SDRAM_ROW; -volatile u8 FW_SDRAM_COL; -volatile u8 FW_CONFIG_MOBILE_SDRAM; -volatile u8 FW_IS_SHARE; - -void load_args(void) -{ - /* Get the fw args from memory. See head1.S for the memory layout. */ - - fw_args = (struct fw_args *)0x80002008; - FW_CPU_ID = fw_args->cpu_id ; - FW_SDRAM_BW16 = fw_args->bus_width; - FW_SDRAM_BANK4 = fw_args->bank_num; - FW_SDRAM_ROW = fw_args->row_addr; - FW_SDRAM_COL = fw_args->col_addr; - FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; - FW_IS_SHARE = fw_args->is_busshare; -} - -/* Initialisation functions. */ - -void gpio_init(void) -{ - /* - * Initialize NAND Flash Pins - */ - __gpio_as_nand(); - - /* - * Initialize SDRAM pins - */ - __gpio_as_sdram_16bit_4720(); -} - -void pll_init(void) -{ - register unsigned int cfcr, plcr1; - int nf, pllout2; - - /* See CPCCR (Clock Control Register). - * 0 == same frequency; 2 == f/3 - */ - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (0 << CPM_CPCCR_CDIV_BIT) | - (2 << CPM_CPCCR_HDIV_BIT) | - (2 << CPM_CPCCR_PDIV_BIT) | - (2 << CPM_CPCCR_MDIV_BIT) | - (2 << CPM_CPCCR_LDIV_BIT); - - /* Init USB Host clock. - * Desired frequency == 48MHz - */ - -#ifdef CONFIG_CPU_JZ4730 - cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); -#else - /* Determine the divider clock output based on the PCS bit. */ - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - - /* Divisor == UHCCDR + 1 */ - REG_CPM_UHCCDR = pllout2 / 48000000 - 1; -#endif - - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* Update PLL and wait. */ - - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; - while (!__cpm_pll_is_on()); -} - -void sdram_init(void) -{ - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - unsigned int pllout = __cpm_get_pllout(); - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - /* Divisors for CPCCR values. */ - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = pllout / div[__cpm_get_cdiv()]; - mem_clk = pllout / div[__cpm_get_mdiv()]; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ - dmcr0 = (0< 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* jz4730 additional measures */ -#ifdef CONFIG_CPU_JZ4730 - if (FW_SDRAM_BW16) - sdmode <<= 1; - else - sdmode <<= 2; -#endif - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - - /* jz4730 additional measures */ -#ifdef CONFIG_CPU_JZ4730 - REG8(EMC_SDMR1|sdmode) = 0; -#endif - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - REG8(EMC_SDMR0|sdmode) = 0; - - /* jz4730 additional measures */ -#ifdef CONFIG_CPU_JZ4730 - REG8(EMC_SDMR1|sdmode) = 0; -#endif - - /* Set back to basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} diff -r 25ad44524ef5 -r a63d68f0b926 stage1/board-nanonote.h --- a/stage1/board-nanonote.h Tue Jun 09 21:26:39 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -#ifndef __BOARD_NANONOTE_H__ -#define __BOARD_NANONOTE_H__ - -/* Initialisation functions. */ - -void load_args(void); -void gpio_init(void); -void pll_init(void); -void sdram_init(void); - -#endif /* __BOARD_NANONOTE_H__ */ diff -r 25ad44524ef5 -r a63d68f0b926 stage1/board.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/board.c Tue Jun 09 21:36:40 2015 +0200 @@ -0,0 +1,231 @@ +/* + * Generic board initialisation, based on uboot-xburst and xburst-tools. + * + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * Copyright (C) 2005-2006 Ingenic Semiconductor, + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifdef CONFIG_CPU_JZ4730 +#include "jz4730.h" +#else +#include "jz4740.h" +#endif + +#include "sdram.h" +#include "usb_boot_defines.h" + +/* These arguments are initialised by usbboot and are defined in... + /etc/xburst-tools/usbboot.cfg. */ + +struct fw_args *fw_args; +volatile u32 FW_CPU_ID; +volatile u8 FW_SDRAM_BW16; +volatile u8 FW_SDRAM_BANK4; +volatile u8 FW_SDRAM_ROW; +volatile u8 FW_SDRAM_COL; +volatile u8 FW_CONFIG_MOBILE_SDRAM; +volatile u8 FW_IS_SHARE; + +void load_args(void) +{ + /* Get the fw args from memory. See head1.S for the memory layout. */ + + fw_args = (struct fw_args *)0x80002008; + FW_CPU_ID = fw_args->cpu_id ; + FW_SDRAM_BW16 = fw_args->bus_width; + FW_SDRAM_BANK4 = fw_args->bank_num; + FW_SDRAM_ROW = fw_args->row_addr; + FW_SDRAM_COL = fw_args->col_addr; + FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; + FW_IS_SHARE = fw_args->is_busshare; +} + +/* Initialisation functions. */ + +void gpio_init(void) +{ + /* + * Initialize NAND Flash Pins + */ + __gpio_as_nand(); + + /* + * Initialize SDRAM pins + */ + __gpio_as_sdram_16bit_4720(); +} + +void pll_init(void) +{ + register unsigned int cfcr, plcr1; + int nf, pllout2; + + /* See CPCCR (Clock Control Register). + * 0 == same frequency; 2 == f/3 + */ + + cfcr = CPM_CPCCR_CLKOEN | + CPM_CPCCR_PCS | + (0 << CPM_CPCCR_CDIV_BIT) | + (2 << CPM_CPCCR_HDIV_BIT) | + (2 << CPM_CPCCR_PDIV_BIT) | + (2 << CPM_CPCCR_MDIV_BIT) | + (2 << CPM_CPCCR_LDIV_BIT); + + /* Init USB Host clock. + * Desired frequency == 48MHz + */ + +#ifdef CONFIG_CPU_JZ4730 + cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); +#else + /* Determine the divider clock output based on the PCS bit. */ + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); + + /* Divisor == UHCCDR + 1 */ + REG_CPM_UHCCDR = pllout2 / 48000000 - 1; +#endif + + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ + CPM_CPPCR_PLLEN; /* enable PLL */ + + /* Update PLL and wait. */ + + REG_CPM_CPCCR = cfcr; + REG_CPM_CPPCR = plcr1; + while (!__cpm_pll_is_on()); +} + +void sdram_init(void) +{ + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; + unsigned int pllout = __cpm_get_pllout(); + + unsigned int cas_latency_sdmr[2] = { + EMC_SDMR_CAS_2, + EMC_SDMR_CAS_3, + }; + + unsigned int cas_latency_dmcr[2] = { + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ + }; + + /* Divisors for CPCCR values. */ + + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + cpu_clk = pllout / div[__cpm_get_cdiv()]; + mem_clk = pllout / div[__cpm_get_mdiv()]; + + REG_EMC_BCR = 0; /* Disable bus release */ + REG_EMC_RTCSR = 0; /* Disable clock for counting */ + + /* Fault DMCR value for mode register setting*/ + dmcr0 = (0< 11) tmp = 11; + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); + tmp = SDRAM_RCD/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_RCD_BIT); + tmp = SDRAM_TPC/ns; + if (tmp > 7) tmp = 7; + dmcr |= (tmp << EMC_DMCR_TPC_BIT); + tmp = SDRAM_TRWL/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_TRWL_BIT); + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; + if (tmp > 14) tmp = 14; + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); + + /* SDRAM mode value */ + sdmode = EMC_SDMR_BT_SEQ | + EMC_SDMR_OM_NORMAL | + EMC_SDMR_BL_4 | + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; + + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + if (FW_SDRAM_BW16) + sdmode <<= 1; + else + sdmode <<= 2; +#endif + + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ + REG_EMC_DMCR = dmcr; + REG8(EMC_SDMR0|sdmode) = 0; + + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + REG8(EMC_SDMR1|sdmode) = 0; +#endif + + /* Wait for precharge, > 200us */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 2. Enable auto-refresh */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; + + tmp = SDRAM_TREF/ns; + tmp = tmp/64 + 1; + if (tmp > 0xff) tmp = 0xff; + REG_EMC_RTCOR = tmp; + REG_EMC_RTCNT = 0; + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ + + /* Wait for number of auto-refresh cycles */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 3. Mode Register Set */ + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + REG8(EMC_SDMR0|sdmode) = 0; + + /* jz4730 additional measures */ +#ifdef CONFIG_CPU_JZ4730 + REG8(EMC_SDMR1|sdmode) = 0; +#endif + + /* Set back to basic DMCR value */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + + /* everything is ok now */ +} diff -r 25ad44524ef5 -r a63d68f0b926 stage1/board.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/board.h Tue Jun 09 21:36:40 2015 +0200 @@ -0,0 +1,11 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +/* Initialisation functions. */ + +void load_args(void); +void gpio_init(void); +void pll_init(void); +void sdram_init(void); + +#endif /* __BOARD_H__ */ diff -r 25ad44524ef5 -r a63d68f0b926 stage1/stage1.c --- a/stage1/stage1.c Tue Jun 09 21:26:39 2015 +0200 +++ b/stage1/stage1.c Tue Jun 09 21:36:40 2015 +0200 @@ -18,7 +18,7 @@ * this program. If not, see . */ -#include "board-nanonote.h" +#include "board.h" void c_main(void) {