1.1 --- a/stage2/Makefile Sun Jun 14 21:14:30 2015 +0200
1.2 +++ b/stage2/Makefile Sun Jun 14 21:17:08 2015 +0200
1.3 @@ -62,8 +62,8 @@
1.4
1.5 # Ordering of objects is important and cannot be left to replacement rules.
1.6
1.7 -SRC = head2.S stage2.c lcd.c jzlcd.c board.c $(BOARD_SRC)
1.8 -OBJ = head2.o stage2.o lcd.o jzlcd.o board.o $(BOARD_OBJ)
1.9 +SRC = head2.S stage2.c cpu.c lcd.c jzlcd.c board.c $(BOARD_SRC)
1.10 +OBJ = head2.o stage2.o cpu.o lcd.o jzlcd.o board.o $(BOARD_OBJ)
1.11
1.12 .PHONY: all clean distclean
1.13
2.1 --- a/stage2/board.c Sun Jun 14 21:14:30 2015 +0200
2.2 +++ b/stage2/board.c Sun Jun 14 21:17:08 2015 +0200
2.3 @@ -1,7 +1,6 @@
2.4 /*
2.5 * Common routines supporting board initialisation.
2.6 *
2.7 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
2.8 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
2.9 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
2.10 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
2.11 @@ -157,63 +156,3 @@
2.12 {
2.13 return TIMER_HZ;
2.14 }
2.15 -
2.16 -/* CPU-specific routines from U-Boot.
2.17 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
2.18 - See: u-boot/arch/mips/include/asm/cacheops.h
2.19 -*/
2.20 -
2.21 -#define Index_Store_Tag_I 0x08
2.22 -#define Index_Writeback_Inv_D 0x15
2.23 -
2.24 -void flush_icache_all(void)
2.25 -{
2.26 - u32 addr, t = 0;
2.27 -
2.28 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
2.29 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
2.30 -
2.31 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
2.32 - addr += CONFIG_SYS_CACHELINE_SIZE) {
2.33 - asm volatile (
2.34 - ".set mips3\n\t"
2.35 - " cache %0, 0(%1)\n\t"
2.36 - ".set mips2\n\t"
2.37 - :
2.38 - : "I" (Index_Store_Tag_I), "r"(addr));
2.39 - }
2.40 -
2.41 - /* invalicate btb */
2.42 - asm volatile (
2.43 - ".set mips32\n\t"
2.44 - "mfc0 %0, $16, 7\n\t"
2.45 - "nop\n\t"
2.46 - "ori %0,2\n\t"
2.47 - "mtc0 %0, $16, 7\n\t"
2.48 - ".set mips2\n\t"
2.49 - :
2.50 - : "r" (t));
2.51 -}
2.52 -
2.53 -void flush_dcache_all(void)
2.54 -{
2.55 - u32 addr;
2.56 -
2.57 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
2.58 - addr += CONFIG_SYS_CACHELINE_SIZE) {
2.59 - asm volatile (
2.60 - ".set mips3\n\t"
2.61 - " cache %0, 0(%1)\n\t"
2.62 - ".set mips2\n\t"
2.63 - :
2.64 - : "I" (Index_Writeback_Inv_D), "r"(addr));
2.65 - }
2.66 -
2.67 - asm volatile ("sync");
2.68 -}
2.69 -
2.70 -void flush_cache_all(void)
2.71 -{
2.72 - flush_dcache_all();
2.73 - flush_icache_all();
2.74 -}
3.1 --- a/stage2/board.h Sun Jun 14 21:14:30 2015 +0200
3.2 +++ b/stage2/board.h Sun Jun 14 21:17:08 2015 +0200
3.3 @@ -4,7 +4,6 @@
3.4 /* Utility functions. */
3.5
3.6 void udelay(unsigned long usec);
3.7 -void flush_cache_all(void);
3.8 unsigned long get_memory_size(void);
3.9
3.10 #ifdef CONFIG_CPU_JZ4730
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/stage2/cpu.c Sun Jun 14 21:17:08 2015 +0200
4.3 @@ -0,0 +1,80 @@
4.4 +/*
4.5 + * CPU-specific routines from U-Boot.
4.6 + * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
4.7 + * See: u-boot/arch/mips/include/asm/cacheops.h
4.8 + *
4.9 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4.10 + *
4.11 + * This program is free software; you can redistribute it and/or
4.12 + * modify it under the terms of the GNU General Public License as
4.13 + * published by the Free Software Foundation; either version 2 of
4.14 + * the License, or (at your option) any later version.
4.15 + *
4.16 + * This program is distributed in the hope that it will be useful,
4.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4.19 + * GNU General Public License for more details.
4.20 + *
4.21 + * You should have received a copy of the GNU General Public License
4.22 + * along with this program; if not, write to the Free Software
4.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
4.24 + * Boston, MA 02110-1301, USA
4.25 + */
4.26 +
4.27 +#include "xburst_types.h"
4.28 +#include "sdram.h"
4.29 +
4.30 +#define Index_Store_Tag_I 0x08
4.31 +#define Index_Writeback_Inv_D 0x15
4.32 +
4.33 +void flush_icache_all(void)
4.34 +{
4.35 + u32 addr, t = 0;
4.36 +
4.37 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
4.38 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
4.39 +
4.40 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
4.41 + addr += CONFIG_SYS_CACHELINE_SIZE) {
4.42 + asm volatile (
4.43 + ".set mips3\n\t"
4.44 + " cache %0, 0(%1)\n\t"
4.45 + ".set mips2\n\t"
4.46 + :
4.47 + : "I" (Index_Store_Tag_I), "r"(addr));
4.48 + }
4.49 +
4.50 + /* invalicate btb */
4.51 + asm volatile (
4.52 + ".set mips32\n\t"
4.53 + "mfc0 %0, $16, 7\n\t"
4.54 + "nop\n\t"
4.55 + "ori %0,2\n\t"
4.56 + "mtc0 %0, $16, 7\n\t"
4.57 + ".set mips2\n\t"
4.58 + :
4.59 + : "r" (t));
4.60 +}
4.61 +
4.62 +void flush_dcache_all(void)
4.63 +{
4.64 + u32 addr;
4.65 +
4.66 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
4.67 + addr += CONFIG_SYS_CACHELINE_SIZE) {
4.68 + asm volatile (
4.69 + ".set mips3\n\t"
4.70 + " cache %0, 0(%1)\n\t"
4.71 + ".set mips2\n\t"
4.72 + :
4.73 + : "I" (Index_Writeback_Inv_D), "r"(addr));
4.74 + }
4.75 +
4.76 + asm volatile ("sync");
4.77 +}
4.78 +
4.79 +void flush_cache_all(void)
4.80 +{
4.81 + flush_dcache_all();
4.82 + flush_icache_all();
4.83 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
5.2 +++ b/stage2/cpu.h Sun Jun 14 21:17:08 2015 +0200
5.3 @@ -0,0 +1,6 @@
5.4 +#ifndef __CPU_H__
5.5 +#define __CPU_H__
5.6 +
5.7 +void flush_cache_all(void);
5.8 +
5.9 +#endif /* __CPU_H__ */
6.1 --- a/stage2/jzlcd.c Sun Jun 14 21:14:30 2015 +0200
6.2 +++ b/stage2/jzlcd.c Sun Jun 14 21:17:08 2015 +0200
6.3 @@ -22,6 +22,7 @@
6.4
6.5 #include "sdram.h"
6.6 #include "jzlcd.h"
6.7 +#include "cpu.h"
6.8 #include "board.h"
6.9
6.10 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)