1.1 --- a/include/configs.h Mon Jun 08 18:10:10 2015 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,51 +0,0 @@
1.4 -/*
1.5 - * device board
1.6 - *
1.7 - * Copyright 2009 (C) Qi Hardware Inc.,
1.8 - * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.9 - *
1.10 - * This program is free software; you can redistribute it and/or
1.11 - * modify it under the terms of the GNU General Public License
1.12 - * version 3 as published by the Free Software Foundation.
1.13 - *
1.14 - * This program is distributed in the hope that it will be useful,
1.15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 - * GNU General Public License for more details.
1.18 - *
1.19 - * You should have received a copy of the GNU General Public License
1.20 - * along with this program; if not, write to the Free Software
1.21 - * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 - * Boston, MA 02110-1301, USA
1.23 - */
1.24 -#ifndef _CONFIGS_H
1.25 -#define _CONFIGS_H
1.26 -
1.27 -/* Here are these common definitions */
1.28 -/* Once your system configration change, just modify the file */
1.29 -
1.30 -#include "xburst_types.h"
1.31 -
1.32 -#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
1.33 -#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
1.34 -/* SDRAM Timings, unit: ns */
1.35 -#define SDRAM_TRAS 45 /* RAS# Active Time */
1.36 -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1.37 -#define SDRAM_TPC 20 /* RAS# Precharge Time */
1.38 -#define SDRAM_TRWL 7 /* Write Latency Time */
1.39 -#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
1.40 -
1.41 -extern volatile u32 CPU_ID;
1.42 -extern volatile u8 SDRAM_BW16;
1.43 -extern volatile u8 SDRAM_BANK4;
1.44 -extern volatile u8 SDRAM_ROW;
1.45 -extern volatile u8 SDRAM_COL;
1.46 -extern volatile u8 CONFIG_MOBILE_SDRAM;
1.47 -extern volatile u32 CFG_CPU_SPEED;
1.48 -extern volatile u8 PHM_DIV;
1.49 -extern volatile u32 CFG_EXTAL;
1.50 -extern volatile u32 CONFIG_BAUDRATE;
1.51 -extern volatile u32 UART_BASE;
1.52 -extern volatile u8 CONFIG_MOBILE_SDRAM;
1.53 -extern volatile u8 IS_SHARE;
1.54 -#endif
2.1 --- a/include/jz4740_lcd.h Mon Jun 08 18:10:10 2015 +0200
2.2 +++ b/include/jz4740_lcd.h Mon Jun 08 18:47:40 2015 +0200
2.3 @@ -21,8 +21,8 @@
2.4 * MA 02111-1307 USA
2.5 */
2.6
2.7 -#ifndef _LCD_H_
2.8 -#define _LCD_H_
2.9 +#ifndef __JZ4740_LCD_H__
2.10 +#define __JZ4740_LCD_H__
2.11
2.12 /*
2.13 * LCD controller stucture for JZSOC: JZ4740
2.14 @@ -61,6 +61,8 @@
2.15
2.16 extern vidinfo_t panel_info;
2.17
2.18 +/* General values for colour depths and framebuffer characteristics. */
2.19 +
2.20 #define LCD_MONOCHROME 0
2.21 #define LCD_COLOR2 1
2.22 #define LCD_COLOR4 2
2.23 @@ -68,11 +70,6 @@
2.24 #define LCD_COLOR16 4
2.25 #define LCD_COLOR32 5
2.26
2.27 -/* Default to 8bpp if bit depth not specified */
2.28 -#ifndef LCD_BPP
2.29 -#define LCD_BPP LCD_COLOR8
2.30 -#endif
2.31 -
2.32 #ifndef PAGE_SIZE
2.33 #define PAGE_SIZE 4096
2.34 #endif
2.35 @@ -81,4 +78,4 @@
2.36 #define NBITS(bit_code) (1 << (bit_code))
2.37 #define NCOLORS(bit_code) (1 << NBITS(bit_code))
2.38
2.39 -#endif /* _LCD_H_ */
2.40 +#endif /* __JZ4740_LCD_H__ */
3.1 --- a/include/nanonote.h Mon Jun 08 18:10:10 2015 +0200
3.2 +++ b/include/nanonote.h Mon Jun 08 18:47:40 2015 +0200
3.3 @@ -1,18 +1,31 @@
3.4 /*
3.5 - * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
3.6 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
3.7 + * Copyright (C) 2009 Qi Hardware Inc.
3.8 + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
3.9 *
3.10 * This program is free software; you can redistribute it and/or
3.11 * modify it under the terms of the GNU General Public License
3.12 * as published by the Free Software Foundation; either version
3.13 * 3 of the License, or (at your option) any later version.
3.14 + *
3.15 + * This program is distributed in the hope that it will be useful,
3.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3.18 + * GNU General Public License for more details.
3.19 + *
3.20 + * You should have received a copy of the GNU General Public License
3.21 + * along with this program; if not, write to the Free Software
3.22 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
3.23 + * Boston, MA 02110-1301, USA
3.24 */
3.25
3.26 /*
3.27 * This file contains the configuration parameters for the NanoNote.
3.28 */
3.29 -#ifndef __CONFIG_NANONOTE_H
3.30 -#define __CONFIG_NANONOTE_H
3.31 +#ifndef __NANONOTE_H__
3.32 +#define __NANONOTE_H__
3.33 +
3.34 +#include "jz4740_lcd.h"
3.35
3.36 /*
3.37 * Display configuration
3.38 @@ -25,6 +38,22 @@
3.39 #define CONFIG_SYS_SDRAM_BASE 0x80000000
3.40
3.41 /*
3.42 + * SDRAM configuration (timings in ns)
3.43 + */
3.44 +#define CONFIG_NR_DRAM_BANKS 1
3.45 +
3.46 +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
3.47 +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
3.48 +#define SDRAM_ROW 13 /* Row address: 11 to 13 */
3.49 +#define SDRAM_COL 9 /* Column address: 8 to 12 */
3.50 +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
3.51 +#define SDRAM_TRAS 45 /* RAS# Active Time */
3.52 +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
3.53 +#define SDRAM_TPC 20 /* RAS# Precharge Time */
3.54 +#define SDRAM_TRWL 7 /* Write Latency Time */
3.55 +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
3.56 +
3.57 +/*
3.58 * Cache configuration
3.59 */
3.60 #define CONFIG_SYS_DCACHE_SIZE 16384
3.61 @@ -61,4 +90,4 @@
3.62 #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
3.63 #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
3.64
3.65 -#endif /* __CONFIG_NANONOTE_H */
3.66 +#endif /* __NANONOTE_H__ */
4.1 --- a/include/xburst_types.h Mon Jun 08 18:10:10 2015 +0200
4.2 +++ b/include/xburst_types.h Mon Jun 08 18:47:40 2015 +0200
4.3 @@ -1,10 +1,21 @@
4.4 /*
4.5 - * Authors: Xiangfu Liu <xiangfu@sharism.cc>
4.6 + * Copyright 2009 (C) Qi Hardware Inc.,
4.7 + * Author: Xiangfu Liu <xiangfu@sharism.cc>
4.8 *
4.9 * This program is free software; you can redistribute it and/or
4.10 * modify it under the terms of the GNU General Public License
4.11 * as published by the Free Software Foundation; either version
4.12 * 3 of the License, or (at your option) any later version.
4.13 + *
4.14 + * This program is distributed in the hope that it will be useful,
4.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4.17 + * GNU General Public License for more details.
4.18 + *
4.19 + * You should have received a copy of the GNU General Public License
4.20 + * along with this program; if not, write to the Free Software
4.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
4.22 + * Boston, MA 02110-1301, USA
4.23 */
4.24
4.25 #ifndef __XBURST_TYPES_H__
5.1 --- a/stage1/board-nanonote.c Mon Jun 08 18:10:10 2015 +0200
5.2 +++ b/stage1/board-nanonote.c Mon Jun 08 18:47:40 2015 +0200
5.3 @@ -21,7 +21,6 @@
5.4 */
5.5
5.6 #include "jz4740.h"
5.7 -#include "configs.h"
5.8 #include "nanonote.h"
5.9 #include "usb_boot_defines.h"
5.10
5.11 @@ -29,26 +28,26 @@
5.12 /etc/xburst-tools/usbboot.cfg. */
5.13
5.14 struct fw_args *fw_args;
5.15 -volatile u32 CPU_ID;
5.16 -volatile u8 SDRAM_BW16;
5.17 -volatile u8 SDRAM_BANK4;
5.18 -volatile u8 SDRAM_ROW;
5.19 -volatile u8 SDRAM_COL;
5.20 -volatile u8 CONFIG_MOBILE_SDRAM;
5.21 -volatile u8 IS_SHARE;
5.22 +volatile u32 FW_CPU_ID;
5.23 +volatile u8 FW_SDRAM_BW16;
5.24 +volatile u8 FW_SDRAM_BANK4;
5.25 +volatile u8 FW_SDRAM_ROW;
5.26 +volatile u8 FW_SDRAM_COL;
5.27 +volatile u8 FW_CONFIG_MOBILE_SDRAM;
5.28 +volatile u8 FW_IS_SHARE;
5.29
5.30 void load_args(void)
5.31 {
5.32 /* Get the fw args from memory. See head1.S for the memory layout. */
5.33
5.34 fw_args = (struct fw_args *)0x80002008;
5.35 - CPU_ID = fw_args->cpu_id ;
5.36 - SDRAM_BW16 = fw_args->bus_width;
5.37 - SDRAM_BANK4 = fw_args->bank_num;
5.38 - SDRAM_ROW = fw_args->row_addr;
5.39 - SDRAM_COL = fw_args->col_addr;
5.40 - CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
5.41 - IS_SHARE = fw_args->is_busshare;
5.42 + FW_CPU_ID = fw_args->cpu_id ;
5.43 + FW_SDRAM_BW16 = fw_args->bus_width;
5.44 + FW_SDRAM_BANK4 = fw_args->bank_num;
5.45 + FW_SDRAM_ROW = fw_args->row_addr;
5.46 + FW_SDRAM_COL = fw_args->col_addr;
5.47 + FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
5.48 + FW_IS_SHARE = fw_args->is_busshare;
5.49 }
5.50
5.51 /* Initialisation functions. */
5.52 @@ -140,15 +139,15 @@
5.53 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
5.54 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
5.55 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
5.56 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
5.57 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
5.58 EMC_DMCR_EPIN |
5.59 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
5.60
5.61 /* Basic DMCR value */
5.62 - dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
5.63 - ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
5.64 - (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
5.65 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
5.66 + dmcr = ((FW_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
5.67 + ((FW_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
5.68 + (FW_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
5.69 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
5.70 EMC_DMCR_EPIN |
5.71 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
5.72
6.1 --- a/stage2/board-nanonote.c Mon Jun 08 18:10:10 2015 +0200
6.2 +++ b/stage2/board-nanonote.c Mon Jun 08 18:47:40 2015 +0200
6.3 @@ -21,7 +21,6 @@
6.4 */
6.5
6.6 #include "jz4740.h"
6.7 -#include "configs.h"
6.8 #include "nanonote.h"
6.9
6.10 /* Later initialisation functions. */
7.1 --- a/stage2/nanonote_gpm940b0.c Mon Jun 08 18:10:10 2015 +0200
7.2 +++ b/stage2/nanonote_gpm940b0.c Mon Jun 08 18:47:40 2015 +0200
7.3 @@ -25,7 +25,6 @@
7.4 /* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */
7.5 #define virt_to_phys(n) ((int) n)
7.6
7.7 -#include "jz4740.h"
7.8 #include "nanonote_gpm940b0.h"
7.9 #include "board-nanonote.h"
7.10
8.1 --- a/stage2/nanonote_gpm940b0.h Mon Jun 08 18:10:10 2015 +0200
8.2 +++ b/stage2/nanonote_gpm940b0.h Mon Jun 08 18:47:40 2015 +0200
8.3 @@ -19,11 +19,10 @@
8.4 * MA 02111-1307 USA
8.5 */
8.6
8.7 -#ifndef __QI_LB60_GPM940B0_H__
8.8 -#define __QI_LB60_GPM940B0_H__
8.9 +#ifndef __NANONOTE_GPM940B0_H__
8.10 +#define __NANONOTE_GPM940B0_H__
8.11
8.12 #include "nanonote.h"
8.13 -#include "jz4740_lcd.h"
8.14 #include "jz4740.h"
8.15
8.16 unsigned long lcd_get_size(void);
8.17 @@ -141,4 +140,4 @@
8.18 __spi_write_reg1(0x05, 0x5e); \
8.19 } while (0)
8.20
8.21 -#endif /* __QI_LB60_GPM940B0_H__ */
8.22 +#endif /* __NANONOTE_GPM940B0_H__ */