1.1 --- a/Makefile Sun Jun 07 20:17:24 2015 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,78 +0,0 @@
1.4 -# Makefile - Build the NanoNote payload
1.5 -#
1.6 -# Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.7 -# Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.8 -#
1.9 -# This program is free software; you can redistribute it and/or modify it under
1.10 -# the terms of the GNU General Public License as published by the Free Software
1.11 -# Foundation; either version 3 of the License, or (at your option) any later
1.12 -# version.
1.13 -#
1.14 -# This program is distributed in the hope that it will be useful, but WITHOUT
1.15 -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
1.16 -# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
1.17 -# details.
1.18 -#
1.19 -# You should have received a copy of the GNU General Public License along with
1.20 -# this program. If not, see <http://www.gnu.org/licenses/>.
1.21 -
1.22 -ARCH = mipsel-linux-gnu
1.23 -CC = $(ARCH)-gcc
1.24 -LD = $(ARCH)-ld
1.25 -NM = $(ARCH)-nm
1.26 -OBJCOPY=$(ARCH)-objcopy
1.27 -OBJDUMP=$(ARCH)-objdump
1.28 -
1.29 -# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably
1.30 -# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work.
1.31 -# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888
1.32 -
1.33 -ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include
1.34 -CFLAGS = -O2 -Wall -fno-unit-at-a-time -fno-zero-initialized-in-bss \
1.35 - -ffreestanding -fno-hosted -fno-builtin \
1.36 - -march=mips32 -mno-abicalls \
1.37 - -Iinclude -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic
1.38 -LDFLAGS = -nostdlib -EL
1.39 -
1.40 -PAYLOAD = stage1.bin stage2.bin
1.41 -TARGET = $(PAYLOAD:.bin=.elf)
1.42 -DUMP = $(PAYLOAD:.bin=.dump)
1.43 -MAP = $(PAYLOAD:.bin=.map)
1.44 -
1.45 -# Ordering of objects is important and cannot be left to replacement rules.
1.46 -
1.47 -SRC1 = head1.S stage1.c board-nanonote.c
1.48 -SRC2 = head2.S stage2.c board-nanonote2.c nanonote_gpm940b0.c lcd.c
1.49 -OBJ1 = head1.o stage1.o board-nanonote.o
1.50 -OBJ2 = head2.o stage2.o board-nanonote2.o nanonote_gpm940b0.o lcd.o
1.51 -OBJ = $(OBJ1) $(OBJ2)
1.52 -
1.53 -.PHONY: all clean distclean
1.54 -
1.55 -all: $(PAYLOAD)
1.56 -
1.57 -clean:
1.58 - rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map
1.59 -
1.60 -distclean: clean
1.61 - echo "Nothing else to clean."
1.62 -
1.63 -$(PAYLOAD): $(TARGET)
1.64 - $(OBJCOPY) -O binary $(@:.bin=.elf) $@+
1.65 - $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump)
1.66 - $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map)
1.67 - $(NM) -n $(@:.bin=.elf) > System-$(@:.bin=.map)
1.68 - chmod -x $@+
1.69 - mv -f $@+ $@
1.70 -
1.71 -stage1.elf: $(OBJ1)
1.72 - $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ1) -o $@
1.73 -
1.74 -stage2.elf: $(OBJ2)
1.75 - $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ2) -o $@
1.76 -
1.77 -.c.o:
1.78 - $(CC) -c $(CFLAGS) $< -o $@
1.79 -
1.80 -.S.o:
1.81 - $(CC) -c $(CFLAGS) $< -o $@
2.1 --- a/board-nanonote.c Sun Jun 07 20:17:24 2015 +0200
2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
2.3 @@ -1,210 +0,0 @@
2.4 -/*
2.5 - * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools.
2.6 - *
2.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
2.8 - * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
2.9 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
2.10 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
2.11 - *
2.12 - * This program is free software; you can redistribute it and/or modify it under
2.13 - * the terms of the GNU General Public License as published by the Free Software
2.14 - * Foundation; either version 3 of the License, or (at your option) any later
2.15 - * version.
2.16 - *
2.17 - * This program is distributed in the hope that it will be useful, but WITHOUT
2.18 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
2.19 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
2.20 - * details.
2.21 - *
2.22 - * You should have received a copy of the GNU General Public License along with
2.23 - * this program. If not, see <http://www.gnu.org/licenses/>.
2.24 - */
2.25 -
2.26 -#include "jz4740.h"
2.27 -#include "configs.h"
2.28 -#include "nanonote.h"
2.29 -#include "usb_boot_defines.h"
2.30 -
2.31 -/* These arguments are initialised by usbboot and are defined in...
2.32 - /etc/xburst-tools/usbboot.cfg. */
2.33 -
2.34 -struct fw_args *fw_args;
2.35 -volatile u32 CPU_ID;
2.36 -volatile u8 SDRAM_BW16;
2.37 -volatile u8 SDRAM_BANK4;
2.38 -volatile u8 SDRAM_ROW;
2.39 -volatile u8 SDRAM_COL;
2.40 -volatile u8 CONFIG_MOBILE_SDRAM;
2.41 -volatile u8 IS_SHARE;
2.42 -
2.43 -void load_args(void)
2.44 -{
2.45 - /* Get the fw args from memory. See head1.S for the memory layout. */
2.46 -
2.47 - fw_args = (struct fw_args *)0x80002008;
2.48 - CPU_ID = fw_args->cpu_id ;
2.49 - SDRAM_BW16 = fw_args->bus_width;
2.50 - SDRAM_BANK4 = fw_args->bank_num;
2.51 - SDRAM_ROW = fw_args->row_addr;
2.52 - SDRAM_COL = fw_args->col_addr;
2.53 - CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
2.54 - IS_SHARE = fw_args->is_busshare;
2.55 -}
2.56 -
2.57 -/* Initialisation functions. */
2.58 -
2.59 -void gpio_init(void)
2.60 -{
2.61 - /*
2.62 - * Initialize NAND Flash Pins
2.63 - */
2.64 - __gpio_as_nand();
2.65 -
2.66 - /*
2.67 - * Initialize SDRAM pins
2.68 - */
2.69 - __gpio_as_sdram_16bit_4720();
2.70 -}
2.71 -
2.72 -void pll_init(void)
2.73 -{
2.74 - register unsigned int cfcr, plcr1;
2.75 - int nf, pllout2;
2.76 -
2.77 - /* See CPCCR (Clock Control Register).
2.78 - * 0 == same frequency; 2 == f/3
2.79 - */
2.80 -
2.81 - cfcr = CPM_CPCCR_CLKOEN |
2.82 - CPM_CPCCR_PCS |
2.83 - (0 << CPM_CPCCR_CDIV_BIT) |
2.84 - (2 << CPM_CPCCR_HDIV_BIT) |
2.85 - (2 << CPM_CPCCR_PDIV_BIT) |
2.86 - (2 << CPM_CPCCR_MDIV_BIT) |
2.87 - (2 << CPM_CPCCR_LDIV_BIT);
2.88 -
2.89 - /* Determine the divider clock output based on the PCS bit. */
2.90 -
2.91 - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
2.92 -
2.93 - /* Init USB Host clock.
2.94 - * Divisor == UHCCDR + 1
2.95 - * Desired frequency == 48MHz
2.96 - */
2.97 -
2.98 - REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
2.99 -
2.100 - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
2.101 - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
2.102 - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
2.103 - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
2.104 - CPM_CPPCR_PLLEN; /* enable PLL */
2.105 -
2.106 - /* Update PLL and wait. */
2.107 -
2.108 - REG_CPM_CPCCR = cfcr;
2.109 - REG_CPM_CPPCR = plcr1;
2.110 - while (!__cpm_pll_is_on());
2.111 -}
2.112 -
2.113 -void sdram_init(void)
2.114 -{
2.115 - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
2.116 - unsigned int pllout = __cpm_get_pllout();
2.117 -
2.118 - unsigned int cas_latency_sdmr[2] = {
2.119 - EMC_SDMR_CAS_2,
2.120 - EMC_SDMR_CAS_3,
2.121 - };
2.122 -
2.123 - unsigned int cas_latency_dmcr[2] = {
2.124 - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
2.125 - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
2.126 - };
2.127 -
2.128 - /* Divisors for CPCCR values. */
2.129 -
2.130 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
2.131 -
2.132 - cpu_clk = pllout / div[__cpm_get_cdiv()];
2.133 - mem_clk = pllout / div[__cpm_get_mdiv()];
2.134 -
2.135 - REG_EMC_BCR = 0; /* Disable bus release */
2.136 - REG_EMC_RTCSR = 0; /* Disable clock for counting */
2.137 -
2.138 - /* Fault DMCR value for mode register setting*/
2.139 -#define SDRAM_ROW0 11
2.140 -#define SDRAM_COL0 8
2.141 -#define SDRAM_BANK40 0
2.142 -
2.143 - dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
2.144 - ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
2.145 - (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
2.146 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.147 - EMC_DMCR_EPIN |
2.148 - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
2.149 -
2.150 - /* Basic DMCR value */
2.151 - dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
2.152 - ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
2.153 - (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
2.154 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.155 - EMC_DMCR_EPIN |
2.156 - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
2.157 -
2.158 - /* SDRAM timimg */
2.159 - ns = 1000000000 / mem_clk;
2.160 - tmp = SDRAM_TRAS/ns;
2.161 - if (tmp < 4) tmp = 4;
2.162 - if (tmp > 11) tmp = 11;
2.163 - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
2.164 - tmp = SDRAM_RCD/ns;
2.165 - if (tmp > 3) tmp = 3;
2.166 - dmcr |= (tmp << EMC_DMCR_RCD_BIT);
2.167 - tmp = SDRAM_TPC/ns;
2.168 - if (tmp > 7) tmp = 7;
2.169 - dmcr |= (tmp << EMC_DMCR_TPC_BIT);
2.170 - tmp = SDRAM_TRWL/ns;
2.171 - if (tmp > 3) tmp = 3;
2.172 - dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
2.173 - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
2.174 - if (tmp > 14) tmp = 14;
2.175 - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
2.176 -
2.177 - /* SDRAM mode value */
2.178 - sdmode = EMC_SDMR_BT_SEQ |
2.179 - EMC_SDMR_OM_NORMAL |
2.180 - EMC_SDMR_BL_4 |
2.181 - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
2.182 -
2.183 - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
2.184 - REG_EMC_DMCR = dmcr;
2.185 - REG8(EMC_SDMR0|sdmode) = 0;
2.186 -
2.187 - /* Wait for precharge, > 200us */
2.188 - tmp = (cpu_clk / 1000000) * 1000;
2.189 - while (tmp--);
2.190 -
2.191 - /* Stage 2. Enable auto-refresh */
2.192 - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
2.193 -
2.194 - tmp = SDRAM_TREF/ns;
2.195 - tmp = tmp/64 + 1;
2.196 - if (tmp > 0xff) tmp = 0xff;
2.197 - REG_EMC_RTCOR = tmp;
2.198 - REG_EMC_RTCNT = 0;
2.199 - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
2.200 -
2.201 - /* Wait for number of auto-refresh cycles */
2.202 - tmp = (cpu_clk / 1000000) * 1000;
2.203 - while (tmp--);
2.204 -
2.205 - /* Stage 3. Mode Register Set */
2.206 - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
2.207 - REG8(EMC_SDMR0|sdmode) = 0;
2.208 -
2.209 - /* Set back to basic DMCR value */
2.210 - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
2.211 -
2.212 - /* everything is ok now */
2.213 -}
3.1 --- a/board-nanonote.h Sun Jun 07 20:17:24 2015 +0200
3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
3.3 @@ -1,11 +0,0 @@
3.4 -#ifndef __BOARD_NANONOTE_H__
3.5 -#define __BOARD_NANONOTE_H__
3.6 -
3.7 -/* Initialisation functions. */
3.8 -
3.9 -void load_args(void);
3.10 -void gpio_init(void);
3.11 -void pll_init(void);
3.12 -void sdram_init(void);
3.13 -
3.14 -#endif /* __BOARD_NANONOTE_H__ */
4.1 --- a/board-nanonote2.c Sun Jun 07 20:17:24 2015 +0200
4.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
4.3 @@ -1,334 +0,0 @@
4.4 -/*
4.5 - * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools.
4.6 - *
4.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
4.8 - * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
4.9 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
4.10 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4.11 - *
4.12 - * This program is free software; you can redistribute it and/or modify it under
4.13 - * the terms of the GNU General Public License as published by the Free Software
4.14 - * Foundation; either version 3 of the License, or (at your option) any later
4.15 - * version.
4.16 - *
4.17 - * This program is distributed in the hope that it will be useful, but WITHOUT
4.18 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
4.19 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
4.20 - * details.
4.21 - *
4.22 - * You should have received a copy of the GNU General Public License along with
4.23 - * this program. If not, see <http://www.gnu.org/licenses/>.
4.24 - */
4.25 -
4.26 -#include "jz4740.h"
4.27 -#include "configs.h"
4.28 -#include "nanonote.h"
4.29 -
4.30 -/* Later initialisation functions. */
4.31 -
4.32 -void gpio_init2(void)
4.33 -{
4.34 - /*
4.35 - * Initialize LCD pins
4.36 - */
4.37 - __gpio_as_slcd_8bit();
4.38 -
4.39 - /*
4.40 - * Initialize MSC pins
4.41 - */
4.42 - __gpio_as_msc();
4.43 -
4.44 - /*
4.45 - * Initialize Other pins
4.46 - */
4.47 - unsigned int i;
4.48 - for (i = 0; i < 7; i++){
4.49 - __gpio_as_input(GPIO_KEYIN_BASE + i);
4.50 - __gpio_enable_pull(GPIO_KEYIN_BASE + i);
4.51 - }
4.52 -
4.53 - for (i = 0; i < 8; i++) {
4.54 - __gpio_as_output(GPIO_KEYOUT_BASE + i);
4.55 - __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
4.56 - }
4.57 -
4.58 - /* enable the TP4, TP5 as UART0 */
4.59 - __gpio_jtag_to_uart0();
4.60 -
4.61 - __gpio_as_input(GPIO_KEYIN_8);
4.62 - __gpio_enable_pull(GPIO_KEYIN_8);
4.63 -
4.64 - __gpio_as_output(GPIO_AUDIO_POP);
4.65 - __gpio_set_pin(GPIO_AUDIO_POP);
4.66 -
4.67 - __gpio_as_output(GPIO_LCD_CS);
4.68 - __gpio_clear_pin(GPIO_LCD_CS);
4.69 -
4.70 - __gpio_as_output(GPIO_AMP_EN);
4.71 - __gpio_clear_pin(GPIO_AMP_EN);
4.72 -
4.73 - __gpio_as_output(GPIO_SDPW_EN);
4.74 - __gpio_disable_pull(GPIO_SDPW_EN);
4.75 - __gpio_clear_pin(GPIO_SDPW_EN);
4.76 -
4.77 - __gpio_as_input(GPIO_SD_DETECT);
4.78 - __gpio_disable_pull(GPIO_SD_DETECT);
4.79 -
4.80 - __gpio_as_input(GPIO_USB_DETECT);
4.81 - __gpio_enable_pull(GPIO_USB_DETECT);
4.82 -}
4.83 -
4.84 -void cpm_init(void)
4.85 -{
4.86 - __cpm_stop_ipu();
4.87 - __cpm_stop_cim();
4.88 - __cpm_stop_i2c();
4.89 - __cpm_stop_ssi();
4.90 - __cpm_stop_uart1();
4.91 - __cpm_stop_sadc();
4.92 - __cpm_stop_uhc();
4.93 - __cpm_stop_udc();
4.94 - __cpm_stop_aic1();
4.95 -/* __cpm_stop_aic2();*/
4.96 -}
4.97 -
4.98 -void rtc_init(void)
4.99 -{
4.100 - while ( !__rtc_write_ready());
4.101 - __rtc_enable_alarm(); /* enable alarm */
4.102 -
4.103 - while ( !__rtc_write_ready());
4.104 - REG_RTC_RGR = 0x00007fff; /* type value */
4.105 -
4.106 - while ( !__rtc_write_ready());
4.107 - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
4.108 -
4.109 - while ( !__rtc_write_ready());
4.110 - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
4.111 -}
4.112 -
4.113 -unsigned long get_memory_size(void)
4.114 -{
4.115 - unsigned int dmcr;
4.116 - unsigned int rows, cols, dw, banks;
4.117 - unsigned long size;
4.118 -
4.119 - dmcr = REG_EMC_DMCR;
4.120 - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
4.121 - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
4.122 - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
4.123 - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
4.124 -
4.125 - size = (1 << (rows + cols)) * dw * banks;
4.126 -
4.127 - return size;
4.128 -}
4.129 -
4.130 -/* Timer routines. */
4.131 -
4.132 -#define TIMER_CHAN 0
4.133 -#define TIMER_FDATA 0xffff /* Timer full data value */
4.134 -#define TIMER_HZ CONFIG_SYS_HZ
4.135 -
4.136 -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
4.137 -
4.138 -static unsigned long timestamp;
4.139 -static unsigned long lastdec;
4.140 -
4.141 -void reset_timer_masked(void);
4.142 -unsigned long get_timer_masked(void);
4.143 -void udelay_masked(unsigned long usec);
4.144 -
4.145 -/*
4.146 - * timer without interrupts
4.147 - */
4.148 -
4.149 -int timer_init(void)
4.150 -{
4.151 - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
4.152 - REG_TCU_TCNT(TIMER_CHAN) = 0;
4.153 - REG_TCU_TDHR(TIMER_CHAN) = 0;
4.154 - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
4.155 -
4.156 - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
4.157 - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
4.158 - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
4.159 -
4.160 - lastdec = 0;
4.161 - timestamp = 0;
4.162 -
4.163 - return 0;
4.164 -}
4.165 -
4.166 -void reset_timer(void)
4.167 -{
4.168 - reset_timer_masked ();
4.169 -}
4.170 -
4.171 -unsigned long get_timer(unsigned long base)
4.172 -{
4.173 - return get_timer_masked () - base;
4.174 -}
4.175 -
4.176 -void set_timer(unsigned long t)
4.177 -{
4.178 - timestamp = t;
4.179 -}
4.180 -
4.181 -void udelay (unsigned long usec)
4.182 -{
4.183 - unsigned long tmo,tmp;
4.184 -
4.185 - /* normalize */
4.186 - if (usec >= 1000) {
4.187 - tmo = usec / 1000;
4.188 - tmo *= TIMER_HZ;
4.189 - tmo /= 1000;
4.190 - }
4.191 - else {
4.192 - if (usec >= 1) {
4.193 - tmo = usec * TIMER_HZ;
4.194 - tmo /= (1000*1000);
4.195 - }
4.196 - else
4.197 - tmo = 1;
4.198 - }
4.199 -
4.200 - /* check for rollover during this delay */
4.201 - tmp = get_timer (0);
4.202 - if ((tmp + tmo) < tmp )
4.203 - reset_timer_masked(); /* timer would roll over */
4.204 - else
4.205 - tmo += tmp;
4.206 -
4.207 - while (get_timer_masked () < tmo);
4.208 -}
4.209 -
4.210 -void reset_timer_masked (void)
4.211 -{
4.212 - /* reset time */
4.213 - lastdec = READ_TIMER;
4.214 - timestamp = 0;
4.215 -}
4.216 -
4.217 -unsigned long get_timer_masked (void)
4.218 -{
4.219 - unsigned long now = READ_TIMER;
4.220 -
4.221 - if (lastdec <= now) {
4.222 - /* normal mode */
4.223 - timestamp += (now - lastdec);
4.224 - } else {
4.225 - /* we have an overflow ... */
4.226 - timestamp += TIMER_FDATA + now - lastdec;
4.227 - }
4.228 - lastdec = now;
4.229 -
4.230 - return timestamp;
4.231 -}
4.232 -
4.233 -void udelay_masked (unsigned long usec)
4.234 -{
4.235 - unsigned long tmo;
4.236 - unsigned long endtime;
4.237 - signed long diff;
4.238 -
4.239 - /* normalize */
4.240 - if (usec >= 1000) {
4.241 - tmo = usec / 1000;
4.242 - tmo *= TIMER_HZ;
4.243 - tmo /= 1000;
4.244 - } else {
4.245 - if (usec > 1) {
4.246 - tmo = usec * TIMER_HZ;
4.247 - tmo /= (1000*1000);
4.248 - } else {
4.249 - tmo = 1;
4.250 - }
4.251 - }
4.252 -
4.253 - endtime = get_timer_masked () + tmo;
4.254 -
4.255 - do {
4.256 - unsigned long now = get_timer_masked ();
4.257 - diff = endtime - now;
4.258 - } while (diff >= 0);
4.259 -}
4.260 -
4.261 -/*
4.262 - * This function is derived from PowerPC code (read timebase as long long).
4.263 - * On MIPS it just returns the timer value.
4.264 - */
4.265 -unsigned long long get_ticks(void)
4.266 -{
4.267 - return get_timer(0);
4.268 -}
4.269 -
4.270 -/*
4.271 - * This function is derived from PowerPC code (timebase clock frequency).
4.272 - * On MIPS it returns the number of timer ticks per second.
4.273 - */
4.274 -unsigned long get_tbclk (void)
4.275 -{
4.276 - return TIMER_HZ;
4.277 -}
4.278 -
4.279 -/* CPU-specific routines from U-Boot.
4.280 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
4.281 - See: u-boot/arch/mips/include/asm/cacheops.h
4.282 -*/
4.283 -
4.284 -#define Index_Store_Tag_I 0x08
4.285 -#define Index_Writeback_Inv_D 0x15
4.286 -
4.287 -void flush_icache_all(void)
4.288 -{
4.289 - u32 addr, t = 0;
4.290 -
4.291 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
4.292 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
4.293 -
4.294 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
4.295 - addr += CONFIG_SYS_CACHELINE_SIZE) {
4.296 - asm volatile (
4.297 - ".set mips3\n\t"
4.298 - " cache %0, 0(%1)\n\t"
4.299 - ".set mips2\n\t"
4.300 - :
4.301 - : "I" (Index_Store_Tag_I), "r"(addr));
4.302 - }
4.303 -
4.304 - /* invalicate btb */
4.305 - asm volatile (
4.306 - ".set mips32\n\t"
4.307 - "mfc0 %0, $16, 7\n\t"
4.308 - "nop\n\t"
4.309 - "ori %0,2\n\t"
4.310 - "mtc0 %0, $16, 7\n\t"
4.311 - ".set mips2\n\t"
4.312 - :
4.313 - : "r" (t));
4.314 -}
4.315 -
4.316 -void flush_dcache_all(void)
4.317 -{
4.318 - u32 addr;
4.319 -
4.320 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
4.321 - addr += CONFIG_SYS_CACHELINE_SIZE) {
4.322 - asm volatile (
4.323 - ".set mips3\n\t"
4.324 - " cache %0, 0(%1)\n\t"
4.325 - ".set mips2\n\t"
4.326 - :
4.327 - : "I" (Index_Writeback_Inv_D), "r"(addr));
4.328 - }
4.329 -
4.330 - asm volatile ("sync");
4.331 -}
4.332 -
4.333 -void flush_cache_all(void)
4.334 -{
4.335 - flush_dcache_all();
4.336 - flush_icache_all();
4.337 -}
5.1 --- a/board-nanonote2.h Sun Jun 07 20:17:24 2015 +0200
5.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
5.3 @@ -1,17 +0,0 @@
5.4 -#ifndef __BOARD_NANONOTE2_H__
5.5 -#define __BOARD_NANONOTE2_H__
5.6 -
5.7 -/* Initialisation functions. */
5.8 -
5.9 -void gpio_init2(void);
5.10 -void cpm_init(void);
5.11 -void rtc_init(void);
5.12 -int timer_init(void);
5.13 -
5.14 -/* Utility functions. */
5.15 -
5.16 -void udelay(unsigned long usec);
5.17 -void flush_cache_all(void);
5.18 -unsigned long get_memory_size(void);
5.19 -
5.20 -#endif /* __BOARD_NANONOTE2_H__ */
6.1 --- a/head1.S Sun Jun 07 20:17:24 2015 +0200
6.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
6.3 @@ -1,52 +0,0 @@
6.4 -/*
6.5 - * Entry point of the firmware.
6.6 - * The firmware code is executed in the ICache.
6.7 - *
6.8 - * Copyright 2009 (C) Qi Hardware Inc.,
6.9 - * Author: Xiangfu Liu <xiangfu@sharism.cc>
6.10 - *
6.11 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
6.12 - *
6.13 - * This program is free software; you can redistribute it and/or
6.14 - * modify it under the terms of the GNU General Public License
6.15 - * version 3 as published by the Free Software Foundation.
6.16 - *
6.17 - * This program is distributed in the hope that it will be useful,
6.18 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6.19 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6.20 - * GNU General Public License for more details.
6.21 - *
6.22 - * You should have received a copy of the GNU General Public License
6.23 - * along with this program; if not, write to the Free Software
6.24 - * Foundation, Inc., 51 Franklin Street, Fifth Floor,
6.25 - * Boston, MA 02110-1301, USA
6.26 - */
6.27 -
6.28 - .text
6.29 -
6.30 - .extern c_main
6.31 -
6.32 - .globl _start
6.33 - .set noreorder
6.34 -_start:
6.35 - b real_start
6.36 - nop
6.37 - .word 0x0 /* address: 0x80002008 */
6.38 - .word 0x0
6.39 - .word 0x0
6.40 - .word 0x0
6.41 - .word 0x0
6.42 - .word 0x0
6.43 - .word 0x0
6.44 - .word 0x0
6.45 - /* reserve 8 words for args sizeof(struct fw_args)
6.46 - */
6.47 -real_start:
6.48 - /*
6.49 - * setup stack, jump to C code
6.50 - */
6.51 - la $29, 0x80004000 /* sp */
6.52 - j c_main
6.53 - nop
6.54 -
6.55 - .set reorder
7.1 --- a/head2.S Sun Jun 07 20:17:24 2015 +0200
7.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
7.3 @@ -1,33 +0,0 @@
7.4 -/*
7.5 - * Entry point of the firmware.
7.6 - * The firmware code are executed in the ICache.
7.7 - * Do not edit!
7.8 - * Copyright (C) 2006 Ingenic Semiconductor Inc.
7.9 - *
7.10 - */
7.11 -
7.12 - .text
7.13 - .extern c_main
7.14 -
7.15 - .globl _start
7.16 - .set noreorder
7.17 -_start:
7.18 - b real_start
7.19 - nop
7.20 - .word 0x0 // its address == start address + 8
7.21 - .word 0x0
7.22 - .word 0x0
7.23 - .word 0x0
7.24 - .word 0x0
7.25 - .word 0x0
7.26 - .word 0x0
7.27 - .word 0x0
7.28 -
7.29 -real_start:
7.30 - /* setup stack, jump to C code */
7.31 - add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0
7.32 - add $25, $20, 0x40 // t9 = c_main()
7.33 - j $25
7.34 - nop
7.35 -
7.36 - .set reorder
8.1 --- a/lcd.c Sun Jun 07 20:17:24 2015 +0200
8.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
8.3 @@ -1,88 +0,0 @@
8.4 -/*
8.5 - * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools.
8.6 - *
8.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
8.8 - * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
8.9 - *
8.10 - * This program is free software; you can redistribute it and/or modify it under
8.11 - * the terms of the GNU General Public License as published by the Free Software
8.12 - * Foundation; either version 3 of the License, or (at your option) any later
8.13 - * version.
8.14 - *
8.15 - * This program is distributed in the hope that it will be useful, but WITHOUT
8.16 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
8.17 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
8.18 - * details.
8.19 - *
8.20 - * You should have received a copy of the GNU General Public License along with
8.21 - * this program. If not, see <http://www.gnu.org/licenses/>.
8.22 - */
8.23 -
8.24 -#include "xburst_types.h"
8.25 -#include "nanonote_gpm940b0.h"
8.26 -#include "board-nanonote2.h"
8.27 -
8.28 -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
8.29 -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
8.30 -
8.31 -unsigned long lcd_setmem(unsigned long addr)
8.32 -{
8.33 - unsigned long size;
8.34 -
8.35 - size = lcd_get_size();
8.36 -
8.37 - /* Round up to nearest full page, or MMU section if defined */
8.38 - size = ALIGN(size, PAGE_SIZE);
8.39 - addr = ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE);
8.40 -
8.41 - /* Allocate pages for the frame buffer. */
8.42 - addr -= size;
8.43 -
8.44 - return addr;
8.45 -}
8.46 -
8.47 -#define N_BLK_VERT 2
8.48 -#define N_BLK_HOR 3
8.49 -
8.50 -static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
8.51 - 0x00ff0000, 0x0000ff00, 0x00ffff00,
8.52 - 0x000000ff, 0x00ff00ff, 0x0000ffff,
8.53 -};
8.54 -
8.55 -static void test_pattern(void *lcd_base)
8.56 -{
8.57 - unsigned short v_max = panel_info.vl_row;
8.58 - unsigned short h_max = panel_info.vl_col;
8.59 - unsigned short v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT;
8.60 - unsigned short h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR;
8.61 - unsigned short v, h;
8.62 - unsigned char *pix = (unsigned char *)lcd_base;
8.63 -
8.64 - /* WARNING: Code silently assumes 8bit/pixel */
8.65 - for (v = 0; v < v_max; ++v) {
8.66 - unsigned char iy = v / v_step;
8.67 - for (h = 0; h < h_max; ++h) {
8.68 - unsigned char ix = N_BLK_HOR * iy + h / h_step;
8.69 - *pix++ = test_colors[ix];
8.70 - }
8.71 - }
8.72 -}
8.73 -
8.74 -void lcd_clear(void *lcd_base)
8.75 -{
8.76 - test_pattern(lcd_base);
8.77 -}
8.78 -
8.79 -/* LCD initialisation. */
8.80 -
8.81 -static void *lcd_base;
8.82 -
8.83 -void lcd_init(void)
8.84 -{
8.85 - /* Start from the top of memory and obtain a framebuffer region. */
8.86 -
8.87 - lcd_base = (void *) lcd_setmem(get_memory_size());
8.88 - lcd_ctrl_init(lcd_base);
8.89 - lcd_clear(lcd_base);
8.90 - lcd_enable();
8.91 -}
9.1 --- a/lcd.h Sun Jun 07 20:17:24 2015 +0200
9.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
9.3 @@ -1,8 +0,0 @@
9.4 -#ifndef __LCD_H__
9.5 -#define __LCD_H__
9.6 -
9.7 -/* Initialisation functions. */
9.8 -
9.9 -void lcd_init(void);
9.10 -
9.11 -#endif /* __LCD_H__ */
10.1 --- a/nanonote_gpm940b0.c Sun Jun 07 20:17:24 2015 +0200
10.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
10.3 @@ -1,403 +0,0 @@
10.4 -/*
10.5 - * JzRISC lcd controller
10.6 - *
10.7 - * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
10.8 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
10.9 - *
10.10 - * This program is free software; you can redistribute it and/or
10.11 - * modify it under the terms of the GNU General Public License as
10.12 - * published by the Free Software Foundation; either version 2 of
10.13 - * the License, or (at your option) any later version.
10.14 - *
10.15 - * This program is distributed in the hope that it will be useful,
10.16 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
10.17 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10.18 - * GNU General Public License for more details.
10.19 - *
10.20 - * You should have received a copy of the GNU General Public License
10.21 - * along with this program; if not, write to the Free Software
10.22 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
10.23 - * MA 02111-1307 USA
10.24 - */
10.25 -
10.26 -/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h
10.27 - via u-boot/arch/mips/include/asm/io.h */
10.28 -#define virt_to_phys(n) (((int) n) & 0x1fffffff)
10.29 -
10.30 -#include "jz4740.h"
10.31 -#include "nanonote_gpm940b0.h"
10.32 -#include "board-nanonote2.h"
10.33 -
10.34 -#define align2(n) (n)=((((n)+1)>>1)<<1)
10.35 -#define align4(n) (n)=((((n)+3)>>2)<<2)
10.36 -#define align8(n) (n)=((((n)+7)>>3)<<3)
10.37 -
10.38 -struct jzfb_info {
10.39 - unsigned int cfg; /* panel mode and pin usage etc. */
10.40 - unsigned int w;
10.41 - unsigned int h;
10.42 - unsigned int bpp; /* bit per pixel */
10.43 - unsigned int fclk; /* frame clk */
10.44 - unsigned int hsw; /* hsync width, in pclk */
10.45 - unsigned int vsw; /* vsync width, in line count */
10.46 - unsigned int elw; /* end of line, in pclk */
10.47 - unsigned int blw; /* begin of line, in pclk */
10.48 - unsigned int efw; /* end of frame, in line count */
10.49 - unsigned int bfw; /* begin of frame, in line count */
10.50 -};
10.51 -
10.52 -static struct jzfb_info jzfb = {
10.53 - MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
10.54 - 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
10.55 -};
10.56 -
10.57 -vidinfo_t panel_info = {
10.58 - 320, 240, LCD_BPP,
10.59 -};
10.60 -
10.61 -unsigned long lcd_get_size(void)
10.62 -{
10.63 - int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
10.64 - return line_length * panel_info.vl_row;
10.65 -}
10.66 -
10.67 -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
10.68 -static void jz_lcd_desc_init(vidinfo_t *vid);
10.69 -static int jz_lcd_hw_init(vidinfo_t *vid);
10.70 -
10.71 -void lcd_ctrl_init (void *lcdbase)
10.72 -{
10.73 - jz_lcd_init_mem(lcdbase, &panel_info);
10.74 - jz_lcd_desc_init(&panel_info);
10.75 - jz_lcd_hw_init(&panel_info);
10.76 -}
10.77 -
10.78 -/*
10.79 - * Before enabled lcd controller, lcd registers should be configured correctly.
10.80 - */
10.81 -void lcd_enable (void)
10.82 -{
10.83 - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
10.84 - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
10.85 -}
10.86 -
10.87 -void lcd_disable (void)
10.88 -{
10.89 - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
10.90 - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
10.91 -}
10.92 -
10.93 -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
10.94 -{
10.95 - unsigned long palette_mem_size;
10.96 - struct jz_fb_info *fbi = &vid->jz_fb;
10.97 - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
10.98 -
10.99 - fbi->screen = (unsigned long)lcdbase;
10.100 - fbi->palette_size = 256;
10.101 - palette_mem_size = fbi->palette_size * sizeof(u16);
10.102 -
10.103 - /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */
10.104 - /* locate palette and descs at end of page following fb */
10.105 - fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
10.106 -
10.107 - return 0;
10.108 -}
10.109 -
10.110 -static void jz_lcd_desc_init(vidinfo_t *vid)
10.111 -{
10.112 - struct jz_fb_info * fbi;
10.113 - fbi = &vid->jz_fb;
10.114 - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
10.115 - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
10.116 - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
10.117 -
10.118 - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
10.119 -
10.120 - /* populate descriptors */
10.121 - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
10.122 - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
10.123 - fbi->dmadesc_fblow->fidr = 0;
10.124 - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
10.125 -
10.126 - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
10.127 -
10.128 - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
10.129 - fbi->dmadesc_fbhigh->fidr = 0;
10.130 - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
10.131 -
10.132 - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
10.133 - fbi->dmadesc_palette->fidr = 0;
10.134 - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
10.135 -
10.136 - if(NBITS(vid->vl_bpix) < 12)
10.137 - {
10.138 - /* assume any mode with <12 bpp is palette driven */
10.139 - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
10.140 - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
10.141 - /* flips back and forth between pal and fbhigh */
10.142 - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
10.143 - } else {
10.144 - /* palette shouldn't be loaded in true-color mode */
10.145 - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
10.146 - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
10.147 - }
10.148 -
10.149 - flush_cache_all();
10.150 -}
10.151 -
10.152 -static int jz_lcd_hw_init(vidinfo_t *vid)
10.153 -{
10.154 - struct jz_fb_info *fbi = &vid->jz_fb;
10.155 - unsigned int val = 0;
10.156 - unsigned int pclk;
10.157 - unsigned int stnH;
10.158 - int pll_div;
10.159 -
10.160 - /* Setting Control register */
10.161 - switch (jzfb.bpp) {
10.162 - case 1:
10.163 - val |= LCD_CTRL_BPP_1;
10.164 - break;
10.165 - case 2:
10.166 - val |= LCD_CTRL_BPP_2;
10.167 - break;
10.168 - case 4:
10.169 - val |= LCD_CTRL_BPP_4;
10.170 - break;
10.171 - case 8:
10.172 - val |= LCD_CTRL_BPP_8;
10.173 - break;
10.174 - case 15:
10.175 - val |= LCD_CTRL_RGB555;
10.176 - case 16:
10.177 - val |= LCD_CTRL_BPP_16;
10.178 - break;
10.179 - case 17 ... 32:
10.180 - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
10.181 - break;
10.182 -
10.183 - default:
10.184 - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */
10.185 - val |= LCD_CTRL_BPP_16;
10.186 - break;
10.187 - }
10.188 -
10.189 - switch (jzfb.cfg & MODE_MASK) {
10.190 - case MODE_STN_MONO_DUAL:
10.191 - case MODE_STN_COLOR_DUAL:
10.192 - case MODE_STN_MONO_SINGLE:
10.193 - case MODE_STN_COLOR_SINGLE:
10.194 - switch (jzfb.bpp) {
10.195 - case 1:
10.196 - /* val |= LCD_CTRL_PEDN; */
10.197 - case 2:
10.198 - val |= LCD_CTRL_FRC_2;
10.199 - break;
10.200 - case 4:
10.201 - val |= LCD_CTRL_FRC_4;
10.202 - break;
10.203 - case 8:
10.204 - default:
10.205 - val |= LCD_CTRL_FRC_16;
10.206 - break;
10.207 - }
10.208 - break;
10.209 - }
10.210 -
10.211 - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
10.212 - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
10.213 -
10.214 - switch (jzfb.cfg & MODE_MASK) {
10.215 - case MODE_STN_MONO_DUAL:
10.216 - case MODE_STN_COLOR_DUAL:
10.217 - case MODE_STN_MONO_SINGLE:
10.218 - case MODE_STN_COLOR_SINGLE:
10.219 - switch (jzfb.cfg & STN_DAT_PINMASK) {
10.220 - case STN_DAT_PIN1:
10.221 - /* Do not adjust the hori-param value. */
10.222 - break;
10.223 - case STN_DAT_PIN2:
10.224 - align2(jzfb.hsw);
10.225 - align2(jzfb.elw);
10.226 - align2(jzfb.blw);
10.227 - break;
10.228 - case STN_DAT_PIN4:
10.229 - align4(jzfb.hsw);
10.230 - align4(jzfb.elw);
10.231 - align4(jzfb.blw);
10.232 - break;
10.233 - case STN_DAT_PIN8:
10.234 - align8(jzfb.hsw);
10.235 - align8(jzfb.elw);
10.236 - align8(jzfb.blw);
10.237 - break;
10.238 - }
10.239 - break;
10.240 - }
10.241 -
10.242 - REG_LCD_CTRL = val;
10.243 -
10.244 - switch (jzfb.cfg & MODE_MASK) {
10.245 - case MODE_STN_MONO_DUAL:
10.246 - case MODE_STN_COLOR_DUAL:
10.247 - case MODE_STN_MONO_SINGLE:
10.248 - case MODE_STN_COLOR_SINGLE:
10.249 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
10.250 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
10.251 - stnH = jzfb.h >> 1;
10.252 - else
10.253 - stnH = jzfb.h;
10.254 -
10.255 - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
10.256 - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
10.257 -
10.258 - /* Screen setting */
10.259 - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
10.260 - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
10.261 - REG_LCD_DAV = (0 << 16) | (stnH);
10.262 -
10.263 - /* AC BIAs signal */
10.264 - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
10.265 -
10.266 - break;
10.267 -
10.268 - case MODE_TFT_GEN:
10.269 - case MODE_TFT_SHARP:
10.270 - case MODE_TFT_CASIO:
10.271 - case MODE_TFT_SAMSUNG:
10.272 - case MODE_8BIT_SERIAL_TFT:
10.273 - case MODE_TFT_18BIT:
10.274 - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
10.275 - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
10.276 - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
10.277 - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
10.278 - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
10.279 - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
10.280 - break;
10.281 - }
10.282 -
10.283 - switch (jzfb.cfg & MODE_MASK) {
10.284 - case MODE_TFT_SAMSUNG:
10.285 - {
10.286 - unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
10.287 - unsigned int rev_s, rev_e, inv_s, inv_e;
10.288 -
10.289 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
10.290 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
10.291 -
10.292 - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
10.293 - tp_s = jzfb.blw + jzfb.w + 1;
10.294 - tp_e = tp_s + 1;
10.295 - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
10.296 - ckv_s = tp_s - pclk/(1000000000/4100);
10.297 - ckv_e = tp_s + total;
10.298 - rev_s = tp_s - 11; /* -11.5 clk */
10.299 - rev_e = rev_s + total;
10.300 - inv_s = tp_s;
10.301 - inv_e = inv_s + total;
10.302 - REG_LCD_CLS = (tp_s << 16) | tp_e;
10.303 - REG_LCD_PS = (ckv_s << 16) | ckv_e;
10.304 - REG_LCD_SPL = (rev_s << 16) | rev_e;
10.305 - REG_LCD_REV = (inv_s << 16) | inv_e;
10.306 - jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
10.307 - break;
10.308 - }
10.309 - case MODE_TFT_SHARP:
10.310 - {
10.311 - unsigned int total, cls_s, cls_e, ps_s, ps_e;
10.312 - unsigned int spl_s, spl_e, rev_s, rev_e;
10.313 - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
10.314 - spl_s = 1;
10.315 - spl_e = spl_s + 1;
10.316 - cls_s = 0;
10.317 - cls_e = total - 60; /* > 4us (pclk = 80ns) */
10.318 - ps_s = cls_s;
10.319 - ps_e = cls_e;
10.320 - rev_s = total - 40; /* > 3us (pclk = 80ns) */
10.321 - rev_e = rev_s + total;
10.322 - jzfb.cfg |= STFT_PSHI;
10.323 - REG_LCD_SPL = (spl_s << 16) | spl_e;
10.324 - REG_LCD_CLS = (cls_s << 16) | cls_e;
10.325 - REG_LCD_PS = (ps_s << 16) | ps_e;
10.326 - REG_LCD_REV = (rev_s << 16) | rev_e;
10.327 - break;
10.328 - }
10.329 - case MODE_TFT_CASIO:
10.330 - break;
10.331 - }
10.332 -
10.333 - /* Configure the LCD panel */
10.334 - REG_LCD_CFG = jzfb.cfg;
10.335 -
10.336 - /* Timing setting */
10.337 - __cpm_stop_lcd();
10.338 -
10.339 - val = jzfb.fclk; /* frame clk */
10.340 - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
10.341 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
10.342 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
10.343 - } else {
10.344 - /* serial mode: Hsync period = 3*Width_Pixel */
10.345 - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
10.346 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
10.347 - }
10.348 -
10.349 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
10.350 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
10.351 - pclk = (pclk * 3);
10.352 -
10.353 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
10.354 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
10.355 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
10.356 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
10.357 - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
10.358 -
10.359 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
10.360 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
10.361 - pclk >>= 1;
10.362 -
10.363 - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
10.364 - pll_div = pll_div ? 1 : 2 ;
10.365 - val = ( __cpm_get_pllout()/pll_div ) / pclk;
10.366 - val--;
10.367 - if ( val > 0x1ff ) {
10.368 - /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */
10.369 - val = 0x1ff;
10.370 - }
10.371 - __cpm_set_pixdiv(val);
10.372 -
10.373 - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
10.374 - if ( val > 150000000 ) {
10.375 - /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */
10.376 - /* printf("Change LCDClock to 150MHz\n"); */
10.377 - val = 150000000;
10.378 - }
10.379 - val = ( __cpm_get_pllout()/pll_div ) / val;
10.380 - val--;
10.381 - if ( val > 0x1f ) {
10.382 - /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */
10.383 - val = 0x1f;
10.384 - }
10.385 - __cpm_set_ldiv( val );
10.386 - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
10.387 -
10.388 - __cpm_start_lcd();
10.389 - udelay(1000);
10.390 -
10.391 - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
10.392 -
10.393 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
10.394 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
10.395 - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
10.396 -
10.397 - return 0;
10.398 -}
10.399 -
10.400 -void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue)
10.401 -{
10.402 -}
10.403 -
10.404 -void lcd_initcolregs (void)
10.405 -{
10.406 -}
11.1 --- a/nanonote_gpm940b0.h Sun Jun 07 20:17:24 2015 +0200
11.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
11.3 @@ -1,143 +0,0 @@
11.4 -/*
11.5 - * JzRISC lcd controller
11.6 - *
11.7 - * Xiangfu Liu <xiangfu@sharism.cc>
11.8 - *
11.9 - * This program is free software; you can redistribute it and/or
11.10 - * modify it under the terms of the GNU General Public License as
11.11 - * published by the Free Software Foundation; either version 2 of
11.12 - * the License, or (at your option) any later version.
11.13 - *
11.14 - * This program is distributed in the hope that it will be useful,
11.15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
11.16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11.17 - * GNU General Public License for more details.
11.18 - *
11.19 - * You should have received a copy of the GNU General Public License
11.20 - * along with this program; if not, write to the Free Software
11.21 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
11.22 - * MA 02111-1307 USA
11.23 - */
11.24 -
11.25 -#ifndef __QI_LB60_GPM940B0_H__
11.26 -#define __QI_LB60_GPM940B0_H__
11.27 -
11.28 -#include "nanonote.h"
11.29 -#include "jz4740_lcd.h"
11.30 -
11.31 -unsigned long lcd_get_size(void);
11.32 -void lcd_ctrl_init(void *lcdbase);
11.33 -void lcd_enable(void);
11.34 -void lcd_disable(void);
11.35 -
11.36 -struct lcd_desc{
11.37 - unsigned int next_desc; /* LCDDAx */
11.38 - unsigned int databuf; /* LCDSAx */
11.39 - unsigned int frame_id; /* LCDFIDx */
11.40 - unsigned int cmd; /* LCDCMDx */
11.41 -};
11.42 -
11.43 -#define MODE_MASK 0x0f
11.44 -#define MODE_TFT_GEN 0x00
11.45 -#define MODE_TFT_SHARP 0x01
11.46 -#define MODE_TFT_CASIO 0x02
11.47 -#define MODE_TFT_SAMSUNG 0x03
11.48 -#define MODE_CCIR656_NONINT 0x04
11.49 -#define MODE_CCIR656_INT 0x05
11.50 -#define MODE_STN_COLOR_SINGLE 0x08
11.51 -#define MODE_STN_MONO_SINGLE 0x09
11.52 -#define MODE_STN_COLOR_DUAL 0x0a
11.53 -#define MODE_STN_MONO_DUAL 0x0b
11.54 -#define MODE_8BIT_SERIAL_TFT 0x0c
11.55 -
11.56 -#define MODE_TFT_18BIT (1<<7)
11.57 -
11.58 -#define STN_DAT_PIN1 (0x00 << 4)
11.59 -#define STN_DAT_PIN2 (0x01 << 4)
11.60 -#define STN_DAT_PIN4 (0x02 << 4)
11.61 -#define STN_DAT_PIN8 (0x03 << 4)
11.62 -#define STN_DAT_PINMASK STN_DAT_PIN8
11.63 -
11.64 -#define STFT_PSHI (1 << 15)
11.65 -#define STFT_CLSHI (1 << 14)
11.66 -#define STFT_SPLHI (1 << 13)
11.67 -#define STFT_REVHI (1 << 12)
11.68 -
11.69 -#define SYNC_MASTER (0 << 16)
11.70 -#define SYNC_SLAVE (1 << 16)
11.71 -
11.72 -#define DE_P (0 << 9)
11.73 -#define DE_N (1 << 9)
11.74 -
11.75 -#define PCLK_P (0 << 10)
11.76 -#define PCLK_N (1 << 10)
11.77 -
11.78 -#define HSYNC_P (0 << 11)
11.79 -#define HSYNC_N (1 << 11)
11.80 -
11.81 -#define VSYNC_P (0 << 8)
11.82 -#define VSYNC_N (1 << 8)
11.83 -
11.84 -#define DATA_NORMAL (0 << 17)
11.85 -#define DATA_INVERSE (1 << 17)
11.86 -
11.87 -
11.88 -/* Jz LCDFB supported I/O controls. */
11.89 -#define FBIOSETBACKLIGHT 0x4688
11.90 -#define FBIODISPON 0x4689
11.91 -#define FBIODISPOFF 0x468a
11.92 -#define FBIORESET 0x468b
11.93 -#define FBIOPRINT_REG 0x468c
11.94 -
11.95 -/*
11.96 - * LCD panel specific definition
11.97 - */
11.98 -#define MODE (0xc9) /* 8bit serial RGB */
11.99 -
11.100 -#define __spi_write_reg1(reg, val) \
11.101 -do { \
11.102 - unsigned char no; \
11.103 - unsigned short value; \
11.104 - unsigned char a=reg; \
11.105 - unsigned char b=val; \
11.106 - __gpio_set_pin(SPEN); \
11.107 - __gpio_set_pin(SPCK); \
11.108 - __gpio_clear_pin(SPDA); \
11.109 - __gpio_clear_pin(SPEN); \
11.110 - value=((a<<8)|(b&0xFF)); \
11.111 - for(no=0;no<16;no++) \
11.112 - { \
11.113 - __gpio_clear_pin(SPCK); \
11.114 - if((value&0x8000)==0x8000) \
11.115 - __gpio_set_pin(SPDA); \
11.116 - else \
11.117 - __gpio_clear_pin(SPDA); \
11.118 - __gpio_set_pin(SPCK); \
11.119 - value=(value<<1); \
11.120 - } \
11.121 - __gpio_set_pin(SPEN); \
11.122 -} while (0)
11.123 -
11.124 -#define __lcd_display_pin_init() \
11.125 -do { \
11.126 - __cpm_start_tcu(); \
11.127 - __gpio_as_output(SPEN); /* use SPDA */ \
11.128 - __gpio_as_output(SPCK); /* use SPCK */ \
11.129 - __gpio_as_output(SPDA); /* use SPDA */ \
11.130 -} while (0)
11.131 -
11.132 -#define __lcd_display_on() \
11.133 -do { \
11.134 - __spi_write_reg1(0x05, 0x1e); \
11.135 - __spi_write_reg1(0x05, 0x5e); \
11.136 - __spi_write_reg1(0x07, 0x8d); \
11.137 - __spi_write_reg1(0x13, 0x01); \
11.138 - __spi_write_reg1(0x05, 0x5f); \
11.139 -} while (0)
11.140 -
11.141 -#define __lcd_display_off() \
11.142 -do { \
11.143 - __spi_write_reg1(0x05, 0x5e); \
11.144 -} while (0)
11.145 -
11.146 -#endif /* __QI_LB60_GPM940B0_H__ */
12.1 --- a/stage1.c Sun Jun 07 20:17:24 2015 +0200
12.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
12.3 @@ -1,29 +0,0 @@
12.4 -/*
12.5 - * Ben NanoNote stage 1 payload test.
12.6 - *
12.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
12.8 - * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
12.9 - *
12.10 - * This program is free software; you can redistribute it and/or modify it under
12.11 - * the terms of the GNU General Public License as published by the Free Software
12.12 - * Foundation; either version 3 of the License, or (at your option) any later
12.13 - * version.
12.14 - *
12.15 - * This program is distributed in the hope that it will be useful, but WITHOUT
12.16 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
12.17 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
12.18 - * details.
12.19 - *
12.20 - * You should have received a copy of the GNU General Public License along with
12.21 - * this program. If not, see <http://www.gnu.org/licenses/>.
12.22 - */
12.23 -
12.24 -#include "board-nanonote.h"
12.25 -
12.26 -void c_main(void)
12.27 -{
12.28 - load_args();
12.29 - gpio_init();
12.30 - pll_init();
12.31 - sdram_init();
12.32 -}
13.1 --- a/stage1.ld Sun Jun 07 20:17:24 2015 +0200
13.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
13.3 @@ -1,31 +0,0 @@
13.4 -OUTPUT_ARCH(mips)
13.5 -ENTRY(_start)
13.6 -MEMORY
13.7 -{
13.8 - ram : ORIGIN = 0x80002000 , LENGTH = 0x100000
13.9 -}
13.10 -
13.11 -SECTIONS
13.12 -{
13.13 - . = ALIGN(4);
13.14 - .text : { *(.text*) } > ram
13.15 -
13.16 - . = ALIGN(4);
13.17 - .rodata : { *(.rodata*) } > ram
13.18 -
13.19 - . = ALIGN(4);
13.20 - .sdata : { *(.sdata*) } > ram
13.21 -
13.22 - . = ALIGN(4);
13.23 - .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
13.24 -
13.25 - _gp = ABSOLUTE(.); /* Base of small data */
13.26 -
13.27 - .got : { *(.got*) } > ram
13.28 -
13.29 - . = ALIGN(4);
13.30 - .sbss : { *(.sbss*) } > ram
13.31 - .bss : { *(.bss*) } > ram
13.32 - . = ALIGN (4);
13.33 -}
13.34 -
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
14.2 +++ b/stage1/Makefile Sun Jun 07 23:06:08 2015 +0200
14.3 @@ -0,0 +1,73 @@
14.4 +# Makefile - Build the NanoNote payload
14.5 +#
14.6 +# Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
14.7 +# Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
14.8 +#
14.9 +# This program is free software; you can redistribute it and/or modify it under
14.10 +# the terms of the GNU General Public License as published by the Free Software
14.11 +# Foundation; either version 3 of the License, or (at your option) any later
14.12 +# version.
14.13 +#
14.14 +# This program is distributed in the hope that it will be useful, but WITHOUT
14.15 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
14.16 +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
14.17 +# details.
14.18 +#
14.19 +# You should have received a copy of the GNU General Public License along with
14.20 +# this program. If not, see <http://www.gnu.org/licenses/>.
14.21 +
14.22 +ARCH = mipsel-linux-gnu
14.23 +CC = $(ARCH)-gcc
14.24 +LD = $(ARCH)-ld
14.25 +NM = $(ARCH)-nm
14.26 +OBJCOPY=$(ARCH)-objcopy
14.27 +OBJDUMP=$(ARCH)-objdump
14.28 +
14.29 +# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably
14.30 +# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work.
14.31 +# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888
14.32 +
14.33 +ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include
14.34 +CFLAGS = -O2 -Wall \
14.35 + -fno-unit-at-a-time -fno-zero-initialized-in-bss \
14.36 + -ffreestanding -fno-hosted -fno-builtin \
14.37 + -march=mips32 \
14.38 + -I../include -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic
14.39 +LDFLAGS = -nostdlib -EL
14.40 +
14.41 +PAYLOAD = stage1.bin
14.42 +TARGET = $(PAYLOAD:.bin=.elf)
14.43 +DUMP = $(PAYLOAD:.bin=.dump)
14.44 +MAP = $(PAYLOAD:.bin=.map)
14.45 +
14.46 +# Ordering of objects is important and cannot be left to replacement rules.
14.47 +
14.48 +SRC = head1.S stage1.c board-nanonote.c
14.49 +OBJ = head1.o stage1.o board-nanonote.o
14.50 +
14.51 +.PHONY: all clean distclean
14.52 +
14.53 +all: $(PAYLOAD)
14.54 +
14.55 +clean:
14.56 + rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map
14.57 +
14.58 +distclean: clean
14.59 + echo "Nothing else to clean."
14.60 +
14.61 +$(PAYLOAD): $(TARGET)
14.62 + $(OBJCOPY) -O binary $(@:.bin=.elf) $@+
14.63 + $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump)
14.64 + $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map)
14.65 + $(NM) -n $(@:.bin=.elf) > System.map
14.66 + chmod -x $@+
14.67 + mv -f $@+ $@
14.68 +
14.69 +stage1.elf: $(OBJ)
14.70 + $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ) -o $@
14.71 +
14.72 +.c.o:
14.73 + $(CC) -c $(CFLAGS) $< -o $@
14.74 +
14.75 +.S.o:
14.76 + $(CC) -c $(CFLAGS) $< -o $@
15.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
15.2 +++ b/stage1/board-nanonote.c Sun Jun 07 23:06:08 2015 +0200
15.3 @@ -0,0 +1,210 @@
15.4 +/*
15.5 + * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools.
15.6 + *
15.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
15.8 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
15.9 + * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
15.10 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
15.11 + *
15.12 + * This program is free software; you can redistribute it and/or modify it under
15.13 + * the terms of the GNU General Public License as published by the Free Software
15.14 + * Foundation; either version 3 of the License, or (at your option) any later
15.15 + * version.
15.16 + *
15.17 + * This program is distributed in the hope that it will be useful, but WITHOUT
15.18 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
15.19 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
15.20 + * details.
15.21 + *
15.22 + * You should have received a copy of the GNU General Public License along with
15.23 + * this program. If not, see <http://www.gnu.org/licenses/>.
15.24 + */
15.25 +
15.26 +#include "jz4740.h"
15.27 +#include "configs.h"
15.28 +#include "nanonote.h"
15.29 +#include "usb_boot_defines.h"
15.30 +
15.31 +/* These arguments are initialised by usbboot and are defined in...
15.32 + /etc/xburst-tools/usbboot.cfg. */
15.33 +
15.34 +struct fw_args *fw_args;
15.35 +volatile u32 CPU_ID;
15.36 +volatile u8 SDRAM_BW16;
15.37 +volatile u8 SDRAM_BANK4;
15.38 +volatile u8 SDRAM_ROW;
15.39 +volatile u8 SDRAM_COL;
15.40 +volatile u8 CONFIG_MOBILE_SDRAM;
15.41 +volatile u8 IS_SHARE;
15.42 +
15.43 +void load_args(void)
15.44 +{
15.45 + /* Get the fw args from memory. See head1.S for the memory layout. */
15.46 +
15.47 + fw_args = (struct fw_args *)0x80002008;
15.48 + CPU_ID = fw_args->cpu_id ;
15.49 + SDRAM_BW16 = fw_args->bus_width;
15.50 + SDRAM_BANK4 = fw_args->bank_num;
15.51 + SDRAM_ROW = fw_args->row_addr;
15.52 + SDRAM_COL = fw_args->col_addr;
15.53 + CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
15.54 + IS_SHARE = fw_args->is_busshare;
15.55 +}
15.56 +
15.57 +/* Initialisation functions. */
15.58 +
15.59 +void gpio_init(void)
15.60 +{
15.61 + /*
15.62 + * Initialize NAND Flash Pins
15.63 + */
15.64 + __gpio_as_nand();
15.65 +
15.66 + /*
15.67 + * Initialize SDRAM pins
15.68 + */
15.69 + __gpio_as_sdram_16bit_4720();
15.70 +}
15.71 +
15.72 +void pll_init(void)
15.73 +{
15.74 + register unsigned int cfcr, plcr1;
15.75 + int nf, pllout2;
15.76 +
15.77 + /* See CPCCR (Clock Control Register).
15.78 + * 0 == same frequency; 2 == f/3
15.79 + */
15.80 +
15.81 + cfcr = CPM_CPCCR_CLKOEN |
15.82 + CPM_CPCCR_PCS |
15.83 + (0 << CPM_CPCCR_CDIV_BIT) |
15.84 + (2 << CPM_CPCCR_HDIV_BIT) |
15.85 + (2 << CPM_CPCCR_PDIV_BIT) |
15.86 + (2 << CPM_CPCCR_MDIV_BIT) |
15.87 + (2 << CPM_CPCCR_LDIV_BIT);
15.88 +
15.89 + /* Determine the divider clock output based on the PCS bit. */
15.90 +
15.91 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
15.92 +
15.93 + /* Init USB Host clock.
15.94 + * Divisor == UHCCDR + 1
15.95 + * Desired frequency == 48MHz
15.96 + */
15.97 +
15.98 + REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
15.99 +
15.100 + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
15.101 + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
15.102 + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
15.103 + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
15.104 + CPM_CPPCR_PLLEN; /* enable PLL */
15.105 +
15.106 + /* Update PLL and wait. */
15.107 +
15.108 + REG_CPM_CPCCR = cfcr;
15.109 + REG_CPM_CPPCR = plcr1;
15.110 + while (!__cpm_pll_is_on());
15.111 +}
15.112 +
15.113 +void sdram_init(void)
15.114 +{
15.115 + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
15.116 + unsigned int pllout = __cpm_get_pllout();
15.117 +
15.118 + unsigned int cas_latency_sdmr[2] = {
15.119 + EMC_SDMR_CAS_2,
15.120 + EMC_SDMR_CAS_3,
15.121 + };
15.122 +
15.123 + unsigned int cas_latency_dmcr[2] = {
15.124 + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
15.125 + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
15.126 + };
15.127 +
15.128 + /* Divisors for CPCCR values. */
15.129 +
15.130 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
15.131 +
15.132 + cpu_clk = pllout / div[__cpm_get_cdiv()];
15.133 + mem_clk = pllout / div[__cpm_get_mdiv()];
15.134 +
15.135 + REG_EMC_BCR = 0; /* Disable bus release */
15.136 + REG_EMC_RTCSR = 0; /* Disable clock for counting */
15.137 +
15.138 + /* Fault DMCR value for mode register setting*/
15.139 +#define SDRAM_ROW0 11
15.140 +#define SDRAM_COL0 8
15.141 +#define SDRAM_BANK40 0
15.142 +
15.143 + dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
15.144 + ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
15.145 + (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
15.146 + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
15.147 + EMC_DMCR_EPIN |
15.148 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
15.149 +
15.150 + /* Basic DMCR value */
15.151 + dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
15.152 + ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
15.153 + (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
15.154 + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
15.155 + EMC_DMCR_EPIN |
15.156 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
15.157 +
15.158 + /* SDRAM timimg */
15.159 + ns = 1000000000 / mem_clk;
15.160 + tmp = SDRAM_TRAS/ns;
15.161 + if (tmp < 4) tmp = 4;
15.162 + if (tmp > 11) tmp = 11;
15.163 + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
15.164 + tmp = SDRAM_RCD/ns;
15.165 + if (tmp > 3) tmp = 3;
15.166 + dmcr |= (tmp << EMC_DMCR_RCD_BIT);
15.167 + tmp = SDRAM_TPC/ns;
15.168 + if (tmp > 7) tmp = 7;
15.169 + dmcr |= (tmp << EMC_DMCR_TPC_BIT);
15.170 + tmp = SDRAM_TRWL/ns;
15.171 + if (tmp > 3) tmp = 3;
15.172 + dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
15.173 + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
15.174 + if (tmp > 14) tmp = 14;
15.175 + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
15.176 +
15.177 + /* SDRAM mode value */
15.178 + sdmode = EMC_SDMR_BT_SEQ |
15.179 + EMC_SDMR_OM_NORMAL |
15.180 + EMC_SDMR_BL_4 |
15.181 + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
15.182 +
15.183 + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
15.184 + REG_EMC_DMCR = dmcr;
15.185 + REG8(EMC_SDMR0|sdmode) = 0;
15.186 +
15.187 + /* Wait for precharge, > 200us */
15.188 + tmp = (cpu_clk / 1000000) * 1000;
15.189 + while (tmp--);
15.190 +
15.191 + /* Stage 2. Enable auto-refresh */
15.192 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
15.193 +
15.194 + tmp = SDRAM_TREF/ns;
15.195 + tmp = tmp/64 + 1;
15.196 + if (tmp > 0xff) tmp = 0xff;
15.197 + REG_EMC_RTCOR = tmp;
15.198 + REG_EMC_RTCNT = 0;
15.199 + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
15.200 +
15.201 + /* Wait for number of auto-refresh cycles */
15.202 + tmp = (cpu_clk / 1000000) * 1000;
15.203 + while (tmp--);
15.204 +
15.205 + /* Stage 3. Mode Register Set */
15.206 + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
15.207 + REG8(EMC_SDMR0|sdmode) = 0;
15.208 +
15.209 + /* Set back to basic DMCR value */
15.210 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
15.211 +
15.212 + /* everything is ok now */
15.213 +}
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
16.2 +++ b/stage1/board-nanonote.h Sun Jun 07 23:06:08 2015 +0200
16.3 @@ -0,0 +1,11 @@
16.4 +#ifndef __BOARD_NANONOTE_H__
16.5 +#define __BOARD_NANONOTE_H__
16.6 +
16.7 +/* Initialisation functions. */
16.8 +
16.9 +void load_args(void);
16.10 +void gpio_init(void);
16.11 +void pll_init(void);
16.12 +void sdram_init(void);
16.13 +
16.14 +#endif /* __BOARD_NANONOTE_H__ */
17.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
17.2 +++ b/stage1/head1.S Sun Jun 07 23:06:08 2015 +0200
17.3 @@ -0,0 +1,52 @@
17.4 +/*
17.5 + * Entry point of the firmware.
17.6 + * The firmware code is executed in the ICache.
17.7 + *
17.8 + * Copyright 2009 (C) Qi Hardware Inc.,
17.9 + * Author: Xiangfu Liu <xiangfu@sharism.cc>
17.10 + *
17.11 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
17.12 + *
17.13 + * This program is free software; you can redistribute it and/or
17.14 + * modify it under the terms of the GNU General Public License
17.15 + * version 3 as published by the Free Software Foundation.
17.16 + *
17.17 + * This program is distributed in the hope that it will be useful,
17.18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
17.19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17.20 + * GNU General Public License for more details.
17.21 + *
17.22 + * You should have received a copy of the GNU General Public License
17.23 + * along with this program; if not, write to the Free Software
17.24 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17.25 + * Boston, MA 02110-1301, USA
17.26 + */
17.27 +
17.28 + .text
17.29 +
17.30 + .extern c_main
17.31 +
17.32 + .globl _start
17.33 + .set noreorder
17.34 +_start:
17.35 + b real_start
17.36 + nop
17.37 + .word 0x0 /* address: 0x80002008 */
17.38 + .word 0x0
17.39 + .word 0x0
17.40 + .word 0x0
17.41 + .word 0x0
17.42 + .word 0x0
17.43 + .word 0x0
17.44 + .word 0x0
17.45 + /* reserve 8 words for args sizeof(struct fw_args)
17.46 + */
17.47 +real_start:
17.48 + /*
17.49 + * setup stack, jump to C code
17.50 + */
17.51 + la $29, 0x80004000 /* sp */
17.52 + j c_main
17.53 + nop
17.54 +
17.55 + .set reorder
18.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
18.2 +++ b/stage1/stage1.c Sun Jun 07 23:06:08 2015 +0200
18.3 @@ -0,0 +1,29 @@
18.4 +/*
18.5 + * Ben NanoNote stage 1 payload test.
18.6 + *
18.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
18.8 + * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
18.9 + *
18.10 + * This program is free software; you can redistribute it and/or modify it under
18.11 + * the terms of the GNU General Public License as published by the Free Software
18.12 + * Foundation; either version 3 of the License, or (at your option) any later
18.13 + * version.
18.14 + *
18.15 + * This program is distributed in the hope that it will be useful, but WITHOUT
18.16 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
18.17 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
18.18 + * details.
18.19 + *
18.20 + * You should have received a copy of the GNU General Public License along with
18.21 + * this program. If not, see <http://www.gnu.org/licenses/>.
18.22 + */
18.23 +
18.24 +#include "board-nanonote.h"
18.25 +
18.26 +void c_main(void)
18.27 +{
18.28 + load_args();
18.29 + gpio_init();
18.30 + pll_init();
18.31 + sdram_init();
18.32 +}
19.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
19.2 +++ b/stage1/stage1.ld Sun Jun 07 23:06:08 2015 +0200
19.3 @@ -0,0 +1,31 @@
19.4 +OUTPUT_ARCH(mips)
19.5 +ENTRY(_start)
19.6 +MEMORY
19.7 +{
19.8 + ram : ORIGIN = 0x80002000 , LENGTH = 0x100000
19.9 +}
19.10 +
19.11 +SECTIONS
19.12 +{
19.13 + . = ALIGN(4);
19.14 + .text : { *(.text*) } > ram
19.15 +
19.16 + . = ALIGN(4);
19.17 + .rodata : { *(.rodata*) } > ram
19.18 +
19.19 + . = ALIGN(4);
19.20 + .sdata : { *(.sdata*) } > ram
19.21 +
19.22 + . = ALIGN(4);
19.23 + .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
19.24 +
19.25 + _gp = ABSOLUTE(.); /* Base of small data */
19.26 +
19.27 + .got : { *(.got*) } > ram
19.28 +
19.29 + . = ALIGN(4);
19.30 + .sbss : { *(.sbss*) } > ram
19.31 + .bss : { *(.bss*) } > ram
19.32 + . = ALIGN (4);
19.33 +}
19.34 +
20.1 --- a/stage2.c Sun Jun 07 20:17:24 2015 +0200
20.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
20.3 @@ -1,31 +0,0 @@
20.4 -/*
20.5 - * Ben NanoNote stage 2 payload test.
20.6 - *
20.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
20.8 - * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
20.9 - *
20.10 - * This program is free software; you can redistribute it and/or modify it under
20.11 - * the terms of the GNU General Public License as published by the Free Software
20.12 - * Foundation; either version 3 of the License, or (at your option) any later
20.13 - * version.
20.14 - *
20.15 - * This program is distributed in the hope that it will be useful, but WITHOUT
20.16 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
20.17 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
20.18 - * details.
20.19 - *
20.20 - * You should have received a copy of the GNU General Public License along with
20.21 - * this program. If not, see <http://www.gnu.org/licenses/>.
20.22 - */
20.23 -
20.24 -#include "board-nanonote2.h"
20.25 -#include "lcd.h"
20.26 -
20.27 -void c_main(void)
20.28 -{
20.29 - gpio_init2();
20.30 - cpm_init();
20.31 - rtc_init();
20.32 - timer_init();
20.33 - lcd_init();
20.34 -}
22.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
22.2 +++ b/stage2/Makefile Sun Jun 07 23:06:08 2015 +0200
22.3 @@ -0,0 +1,73 @@
22.4 +# Makefile - Build the NanoNote payload
22.5 +#
22.6 +# Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
22.7 +# Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
22.8 +#
22.9 +# This program is free software; you can redistribute it and/or modify it under
22.10 +# the terms of the GNU General Public License as published by the Free Software
22.11 +# Foundation; either version 3 of the License, or (at your option) any later
22.12 +# version.
22.13 +#
22.14 +# This program is distributed in the hope that it will be useful, but WITHOUT
22.15 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
22.16 +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
22.17 +# details.
22.18 +#
22.19 +# You should have received a copy of the GNU General Public License along with
22.20 +# this program. If not, see <http://www.gnu.org/licenses/>.
22.21 +
22.22 +ARCH = mipsel-linux-gnu
22.23 +CC = $(ARCH)-gcc
22.24 +LD = $(ARCH)-ld
22.25 +NM = $(ARCH)-nm
22.26 +OBJCOPY=$(ARCH)-objcopy
22.27 +OBJDUMP=$(ARCH)-objdump
22.28 +
22.29 +# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably
22.30 +# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work.
22.31 +# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888
22.32 +
22.33 +ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include
22.34 +CFLAGS = -O2 -Wall \
22.35 + -fno-unit-at-a-time -fno-zero-initialized-in-bss \
22.36 + -ffreestanding -fno-hosted -fno-builtin \
22.37 + -march=mips32 -fPIC \
22.38 + -I../include -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic
22.39 +LDFLAGS = -nostdlib -EL -pie
22.40 +
22.41 +PAYLOAD = stage2.bin
22.42 +TARGET = $(PAYLOAD:.bin=.elf)
22.43 +DUMP = $(PAYLOAD:.bin=.dump)
22.44 +MAP = $(PAYLOAD:.bin=.map)
22.45 +
22.46 +# Ordering of objects is important and cannot be left to replacement rules.
22.47 +
22.48 +SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c
22.49 +OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o
22.50 +
22.51 +.PHONY: all clean distclean
22.52 +
22.53 +all: $(PAYLOAD)
22.54 +
22.55 +clean:
22.56 + rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map
22.57 +
22.58 +distclean: clean
22.59 + echo "Nothing else to clean."
22.60 +
22.61 +$(PAYLOAD): $(TARGET)
22.62 + $(OBJCOPY) -O binary $(@:.bin=.elf) $@+
22.63 + $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump)
22.64 + $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map)
22.65 + $(NM) -n $(@:.bin=.elf) > System.map
22.66 + chmod -x $@+
22.67 + mv -f $@+ $@
22.68 +
22.69 +stage2.elf: $(OBJ)
22.70 + $(LD) $(LDFLAGS) -pie -T $(@:.elf=.ld) $(OBJ) -o $@
22.71 +
22.72 +.c.o:
22.73 + $(CC) -c $(CFLAGS) $< -o $@
22.74 +
22.75 +.S.o:
22.76 + $(CC) -c $(CFLAGS) $< -o $@
23.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
23.2 +++ b/stage2/board-nanonote.c Sun Jun 07 23:06:08 2015 +0200
23.3 @@ -0,0 +1,334 @@
23.4 +/*
23.5 + * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools.
23.6 + *
23.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
23.8 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
23.9 + * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
23.10 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
23.11 + *
23.12 + * This program is free software; you can redistribute it and/or modify it under
23.13 + * the terms of the GNU General Public License as published by the Free Software
23.14 + * Foundation; either version 3 of the License, or (at your option) any later
23.15 + * version.
23.16 + *
23.17 + * This program is distributed in the hope that it will be useful, but WITHOUT
23.18 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
23.19 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
23.20 + * details.
23.21 + *
23.22 + * You should have received a copy of the GNU General Public License along with
23.23 + * this program. If not, see <http://www.gnu.org/licenses/>.
23.24 + */
23.25 +
23.26 +#include "jz4740.h"
23.27 +#include "configs.h"
23.28 +#include "nanonote.h"
23.29 +
23.30 +/* Later initialisation functions. */
23.31 +
23.32 +void gpio_init2(void)
23.33 +{
23.34 + /*
23.35 + * Initialize LCD pins
23.36 + */
23.37 + __gpio_as_slcd_8bit();
23.38 +
23.39 + /*
23.40 + * Initialize MSC pins
23.41 + */
23.42 + __gpio_as_msc();
23.43 +
23.44 + /*
23.45 + * Initialize Other pins
23.46 + */
23.47 + unsigned int i;
23.48 + for (i = 0; i < 7; i++){
23.49 + __gpio_as_input(GPIO_KEYIN_BASE + i);
23.50 + __gpio_enable_pull(GPIO_KEYIN_BASE + i);
23.51 + }
23.52 +
23.53 + for (i = 0; i < 8; i++) {
23.54 + __gpio_as_output(GPIO_KEYOUT_BASE + i);
23.55 + __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
23.56 + }
23.57 +
23.58 + /* enable the TP4, TP5 as UART0 */
23.59 + __gpio_jtag_to_uart0();
23.60 +
23.61 + __gpio_as_input(GPIO_KEYIN_8);
23.62 + __gpio_enable_pull(GPIO_KEYIN_8);
23.63 +
23.64 + __gpio_as_output(GPIO_AUDIO_POP);
23.65 + __gpio_set_pin(GPIO_AUDIO_POP);
23.66 +
23.67 + __gpio_as_output(GPIO_LCD_CS);
23.68 + __gpio_clear_pin(GPIO_LCD_CS);
23.69 +
23.70 + __gpio_as_output(GPIO_AMP_EN);
23.71 + __gpio_clear_pin(GPIO_AMP_EN);
23.72 +
23.73 + __gpio_as_output(GPIO_SDPW_EN);
23.74 + __gpio_disable_pull(GPIO_SDPW_EN);
23.75 + __gpio_clear_pin(GPIO_SDPW_EN);
23.76 +
23.77 + __gpio_as_input(GPIO_SD_DETECT);
23.78 + __gpio_disable_pull(GPIO_SD_DETECT);
23.79 +
23.80 + __gpio_as_input(GPIO_USB_DETECT);
23.81 + __gpio_enable_pull(GPIO_USB_DETECT);
23.82 +}
23.83 +
23.84 +void cpm_init(void)
23.85 +{
23.86 + __cpm_stop_ipu();
23.87 + __cpm_stop_cim();
23.88 + __cpm_stop_i2c();
23.89 + __cpm_stop_ssi();
23.90 + __cpm_stop_uart1();
23.91 + __cpm_stop_sadc();
23.92 + __cpm_stop_uhc();
23.93 + __cpm_stop_udc();
23.94 + __cpm_stop_aic1();
23.95 +/* __cpm_stop_aic2();*/
23.96 +}
23.97 +
23.98 +void rtc_init(void)
23.99 +{
23.100 + while ( !__rtc_write_ready());
23.101 + __rtc_enable_alarm(); /* enable alarm */
23.102 +
23.103 + while ( !__rtc_write_ready());
23.104 + REG_RTC_RGR = 0x00007fff; /* type value */
23.105 +
23.106 + while ( !__rtc_write_ready());
23.107 + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
23.108 +
23.109 + while ( !__rtc_write_ready());
23.110 + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
23.111 +}
23.112 +
23.113 +unsigned long get_memory_size(void)
23.114 +{
23.115 + unsigned int dmcr;
23.116 + unsigned int rows, cols, dw, banks;
23.117 + unsigned long size;
23.118 +
23.119 + dmcr = REG_EMC_DMCR;
23.120 + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
23.121 + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
23.122 + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
23.123 + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
23.124 +
23.125 + size = (1 << (rows + cols)) * dw * banks;
23.126 +
23.127 + return size;
23.128 +}
23.129 +
23.130 +/* Timer routines. */
23.131 +
23.132 +#define TIMER_CHAN 0
23.133 +#define TIMER_FDATA 0xffff /* Timer full data value */
23.134 +#define TIMER_HZ CONFIG_SYS_HZ
23.135 +
23.136 +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
23.137 +
23.138 +static unsigned long timestamp;
23.139 +static unsigned long lastdec;
23.140 +
23.141 +void reset_timer_masked(void);
23.142 +unsigned long get_timer_masked(void);
23.143 +void udelay_masked(unsigned long usec);
23.144 +
23.145 +/*
23.146 + * timer without interrupts
23.147 + */
23.148 +
23.149 +int timer_init(void)
23.150 +{
23.151 + REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
23.152 + REG_TCU_TCNT(TIMER_CHAN) = 0;
23.153 + REG_TCU_TDHR(TIMER_CHAN) = 0;
23.154 + REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
23.155 +
23.156 + REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
23.157 + REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
23.158 + REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
23.159 +
23.160 + lastdec = 0;
23.161 + timestamp = 0;
23.162 +
23.163 + return 0;
23.164 +}
23.165 +
23.166 +void reset_timer(void)
23.167 +{
23.168 + reset_timer_masked ();
23.169 +}
23.170 +
23.171 +unsigned long get_timer(unsigned long base)
23.172 +{
23.173 + return get_timer_masked () - base;
23.174 +}
23.175 +
23.176 +void set_timer(unsigned long t)
23.177 +{
23.178 + timestamp = t;
23.179 +}
23.180 +
23.181 +void udelay (unsigned long usec)
23.182 +{
23.183 + unsigned long tmo,tmp;
23.184 +
23.185 + /* normalize */
23.186 + if (usec >= 1000) {
23.187 + tmo = usec / 1000;
23.188 + tmo *= TIMER_HZ;
23.189 + tmo /= 1000;
23.190 + }
23.191 + else {
23.192 + if (usec >= 1) {
23.193 + tmo = usec * TIMER_HZ;
23.194 + tmo /= (1000*1000);
23.195 + }
23.196 + else
23.197 + tmo = 1;
23.198 + }
23.199 +
23.200 + /* check for rollover during this delay */
23.201 + tmp = get_timer (0);
23.202 + if ((tmp + tmo) < tmp )
23.203 + reset_timer_masked(); /* timer would roll over */
23.204 + else
23.205 + tmo += tmp;
23.206 +
23.207 + while (get_timer_masked () < tmo);
23.208 +}
23.209 +
23.210 +void reset_timer_masked (void)
23.211 +{
23.212 + /* reset time */
23.213 + lastdec = READ_TIMER;
23.214 + timestamp = 0;
23.215 +}
23.216 +
23.217 +unsigned long get_timer_masked (void)
23.218 +{
23.219 + unsigned long now = READ_TIMER;
23.220 +
23.221 + if (lastdec <= now) {
23.222 + /* normal mode */
23.223 + timestamp += (now - lastdec);
23.224 + } else {
23.225 + /* we have an overflow ... */
23.226 + timestamp += TIMER_FDATA + now - lastdec;
23.227 + }
23.228 + lastdec = now;
23.229 +
23.230 + return timestamp;
23.231 +}
23.232 +
23.233 +void udelay_masked (unsigned long usec)
23.234 +{
23.235 + unsigned long tmo;
23.236 + unsigned long endtime;
23.237 + signed long diff;
23.238 +
23.239 + /* normalize */
23.240 + if (usec >= 1000) {
23.241 + tmo = usec / 1000;
23.242 + tmo *= TIMER_HZ;
23.243 + tmo /= 1000;
23.244 + } else {
23.245 + if (usec > 1) {
23.246 + tmo = usec * TIMER_HZ;
23.247 + tmo /= (1000*1000);
23.248 + } else {
23.249 + tmo = 1;
23.250 + }
23.251 + }
23.252 +
23.253 + endtime = get_timer_masked () + tmo;
23.254 +
23.255 + do {
23.256 + unsigned long now = get_timer_masked ();
23.257 + diff = endtime - now;
23.258 + } while (diff >= 0);
23.259 +}
23.260 +
23.261 +/*
23.262 + * This function is derived from PowerPC code (read timebase as long long).
23.263 + * On MIPS it just returns the timer value.
23.264 + */
23.265 +unsigned long long get_ticks(void)
23.266 +{
23.267 + return get_timer(0);
23.268 +}
23.269 +
23.270 +/*
23.271 + * This function is derived from PowerPC code (timebase clock frequency).
23.272 + * On MIPS it returns the number of timer ticks per second.
23.273 + */
23.274 +unsigned long get_tbclk (void)
23.275 +{
23.276 + return TIMER_HZ;
23.277 +}
23.278 +
23.279 +/* CPU-specific routines from U-Boot.
23.280 + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
23.281 + See: u-boot/arch/mips/include/asm/cacheops.h
23.282 +*/
23.283 +
23.284 +#define Index_Store_Tag_I 0x08
23.285 +#define Index_Writeback_Inv_D 0x15
23.286 +
23.287 +void flush_icache_all(void)
23.288 +{
23.289 + u32 addr, t = 0;
23.290 +
23.291 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
23.292 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
23.293 +
23.294 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
23.295 + addr += CONFIG_SYS_CACHELINE_SIZE) {
23.296 + asm volatile (
23.297 + ".set mips3\n\t"
23.298 + " cache %0, 0(%1)\n\t"
23.299 + ".set mips2\n\t"
23.300 + :
23.301 + : "I" (Index_Store_Tag_I), "r"(addr));
23.302 + }
23.303 +
23.304 + /* invalicate btb */
23.305 + asm volatile (
23.306 + ".set mips32\n\t"
23.307 + "mfc0 %0, $16, 7\n\t"
23.308 + "nop\n\t"
23.309 + "ori %0,2\n\t"
23.310 + "mtc0 %0, $16, 7\n\t"
23.311 + ".set mips2\n\t"
23.312 + :
23.313 + : "r" (t));
23.314 +}
23.315 +
23.316 +void flush_dcache_all(void)
23.317 +{
23.318 + u32 addr;
23.319 +
23.320 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
23.321 + addr += CONFIG_SYS_CACHELINE_SIZE) {
23.322 + asm volatile (
23.323 + ".set mips3\n\t"
23.324 + " cache %0, 0(%1)\n\t"
23.325 + ".set mips2\n\t"
23.326 + :
23.327 + : "I" (Index_Writeback_Inv_D), "r"(addr));
23.328 + }
23.329 +
23.330 + asm volatile ("sync");
23.331 +}
23.332 +
23.333 +void flush_cache_all(void)
23.334 +{
23.335 + flush_dcache_all();
23.336 + flush_icache_all();
23.337 +}
24.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
24.2 +++ b/stage2/board-nanonote.h Sun Jun 07 23:06:08 2015 +0200
24.3 @@ -0,0 +1,17 @@
24.4 +#ifndef __BOARD_NANONOTE2_H__
24.5 +#define __BOARD_NANONOTE2_H__
24.6 +
24.7 +/* Initialisation functions. */
24.8 +
24.9 +void gpio_init2(void);
24.10 +void cpm_init(void);
24.11 +void rtc_init(void);
24.12 +int timer_init(void);
24.13 +
24.14 +/* Utility functions. */
24.15 +
24.16 +void udelay(unsigned long usec);
24.17 +void flush_cache_all(void);
24.18 +unsigned long get_memory_size(void);
24.19 +
24.20 +#endif /* __BOARD_NANONOTE2_H__ */
25.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
25.2 +++ b/stage2/head2.S Sun Jun 07 23:06:08 2015 +0200
25.3 @@ -0,0 +1,33 @@
25.4 +/*
25.5 + * Entry point of the firmware.
25.6 + * The firmware code are executed in the ICache.
25.7 + * Do not edit!
25.8 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
25.9 + *
25.10 + */
25.11 +
25.12 + .text
25.13 + .extern c_main
25.14 +
25.15 + .globl _start
25.16 + .set noreorder
25.17 +_start:
25.18 + b real_start
25.19 + nop
25.20 + .word 0x0 // its address == start address + 8
25.21 + .word 0x0
25.22 + .word 0x0
25.23 + .word 0x0
25.24 + .word 0x0
25.25 + .word 0x0
25.26 + .word 0x0
25.27 + .word 0x0
25.28 +
25.29 +real_start:
25.30 + /* setup stack, jump to C code */
25.31 + add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0
25.32 + add $25, $20, 0x40 // t9 = c_main()
25.33 + j $25
25.34 + nop
25.35 +
25.36 + .set reorder
26.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
26.2 +++ b/stage2/lcd.c Sun Jun 07 23:06:08 2015 +0200
26.3 @@ -0,0 +1,88 @@
26.4 +/*
26.5 + * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools.
26.6 + *
26.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
26.8 + * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
26.9 + *
26.10 + * This program is free software; you can redistribute it and/or modify it under
26.11 + * the terms of the GNU General Public License as published by the Free Software
26.12 + * Foundation; either version 3 of the License, or (at your option) any later
26.13 + * version.
26.14 + *
26.15 + * This program is distributed in the hope that it will be useful, but WITHOUT
26.16 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
26.17 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
26.18 + * details.
26.19 + *
26.20 + * You should have received a copy of the GNU General Public License along with
26.21 + * this program. If not, see <http://www.gnu.org/licenses/>.
26.22 + */
26.23 +
26.24 +#include "xburst_types.h"
26.25 +#include "nanonote_gpm940b0.h"
26.26 +#include "board-nanonote.h"
26.27 +
26.28 +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
26.29 +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
26.30 +
26.31 +unsigned long lcd_setmem(unsigned long addr)
26.32 +{
26.33 + unsigned long size;
26.34 +
26.35 + size = lcd_get_size();
26.36 +
26.37 + /* Round up to nearest full page, or MMU section if defined */
26.38 + size = ALIGN(size, PAGE_SIZE);
26.39 + addr = ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE);
26.40 +
26.41 + /* Allocate pages for the frame buffer. */
26.42 + addr -= size;
26.43 +
26.44 + return addr;
26.45 +}
26.46 +
26.47 +#define N_BLK_VERT 2
26.48 +#define N_BLK_HOR 3
26.49 +
26.50 +static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
26.51 + 0x00ff0000, 0x0000ff00, 0x00ffff00,
26.52 + 0x000000ff, 0x00ff00ff, 0x0000ffff,
26.53 +};
26.54 +
26.55 +static void test_pattern(void *lcd_base)
26.56 +{
26.57 + unsigned short v_max = panel_info.vl_row;
26.58 + unsigned short h_max = panel_info.vl_col;
26.59 + unsigned short v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT;
26.60 + unsigned short h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR;
26.61 + unsigned short v, h;
26.62 + unsigned char *pix = (unsigned char *)lcd_base;
26.63 +
26.64 + /* WARNING: Code silently assumes 8bit/pixel */
26.65 + for (v = 0; v < v_max; ++v) {
26.66 + unsigned char iy = v / v_step;
26.67 + for (h = 0; h < h_max; ++h) {
26.68 + unsigned char ix = N_BLK_HOR * iy + h / h_step;
26.69 + *pix++ = test_colors[ix];
26.70 + }
26.71 + }
26.72 +}
26.73 +
26.74 +void lcd_clear(void *lcd_base)
26.75 +{
26.76 + test_pattern(lcd_base);
26.77 +}
26.78 +
26.79 +/* LCD initialisation. */
26.80 +
26.81 +static void *lcd_base;
26.82 +
26.83 +void lcd_init(void)
26.84 +{
26.85 + /* Start from the top of memory and obtain a framebuffer region. */
26.86 +
26.87 + lcd_base = (void *) lcd_setmem(get_memory_size());
26.88 + lcd_ctrl_init(lcd_base);
26.89 + lcd_clear(lcd_base);
26.90 + lcd_enable();
26.91 +}
27.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
27.2 +++ b/stage2/lcd.h Sun Jun 07 23:06:08 2015 +0200
27.3 @@ -0,0 +1,8 @@
27.4 +#ifndef __LCD_H__
27.5 +#define __LCD_H__
27.6 +
27.7 +/* Initialisation functions. */
27.8 +
27.9 +void lcd_init(void);
27.10 +
27.11 +#endif /* __LCD_H__ */
28.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
28.2 +++ b/stage2/nanonote_gpm940b0.c Sun Jun 07 23:06:08 2015 +0200
28.3 @@ -0,0 +1,403 @@
28.4 +/*
28.5 + * JzRISC lcd controller
28.6 + *
28.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
28.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
28.9 + *
28.10 + * This program is free software; you can redistribute it and/or
28.11 + * modify it under the terms of the GNU General Public License as
28.12 + * published by the Free Software Foundation; either version 2 of
28.13 + * the License, or (at your option) any later version.
28.14 + *
28.15 + * This program is distributed in the hope that it will be useful,
28.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
28.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28.18 + * GNU General Public License for more details.
28.19 + *
28.20 + * You should have received a copy of the GNU General Public License
28.21 + * along with this program; if not, write to the Free Software
28.22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28.23 + * MA 02111-1307 USA
28.24 + */
28.25 +
28.26 +/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h
28.27 + via u-boot/arch/mips/include/asm/io.h */
28.28 +#define virt_to_phys(n) (((int) n) & 0x1fffffff)
28.29 +
28.30 +#include "jz4740.h"
28.31 +#include "nanonote_gpm940b0.h"
28.32 +#include "board-nanonote.h"
28.33 +
28.34 +#define align2(n) (n)=((((n)+1)>>1)<<1)
28.35 +#define align4(n) (n)=((((n)+3)>>2)<<2)
28.36 +#define align8(n) (n)=((((n)+7)>>3)<<3)
28.37 +
28.38 +struct jzfb_info {
28.39 + unsigned int cfg; /* panel mode and pin usage etc. */
28.40 + unsigned int w;
28.41 + unsigned int h;
28.42 + unsigned int bpp; /* bit per pixel */
28.43 + unsigned int fclk; /* frame clk */
28.44 + unsigned int hsw; /* hsync width, in pclk */
28.45 + unsigned int vsw; /* vsync width, in line count */
28.46 + unsigned int elw; /* end of line, in pclk */
28.47 + unsigned int blw; /* begin of line, in pclk */
28.48 + unsigned int efw; /* end of frame, in line count */
28.49 + unsigned int bfw; /* begin of frame, in line count */
28.50 +};
28.51 +
28.52 +static struct jzfb_info jzfb = {
28.53 + MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
28.54 + 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
28.55 +};
28.56 +
28.57 +vidinfo_t panel_info = {
28.58 + 320, 240, LCD_BPP,
28.59 +};
28.60 +
28.61 +unsigned long lcd_get_size(void)
28.62 +{
28.63 + int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
28.64 + return line_length * panel_info.vl_row;
28.65 +}
28.66 +
28.67 +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
28.68 +static void jz_lcd_desc_init(vidinfo_t *vid);
28.69 +static int jz_lcd_hw_init(vidinfo_t *vid);
28.70 +
28.71 +void lcd_ctrl_init (void *lcdbase)
28.72 +{
28.73 + jz_lcd_init_mem(lcdbase, &panel_info);
28.74 + jz_lcd_desc_init(&panel_info);
28.75 + jz_lcd_hw_init(&panel_info);
28.76 +}
28.77 +
28.78 +/*
28.79 + * Before enabled lcd controller, lcd registers should be configured correctly.
28.80 + */
28.81 +void lcd_enable (void)
28.82 +{
28.83 + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
28.84 + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
28.85 +}
28.86 +
28.87 +void lcd_disable (void)
28.88 +{
28.89 + REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
28.90 + /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
28.91 +}
28.92 +
28.93 +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
28.94 +{
28.95 + unsigned long palette_mem_size;
28.96 + struct jz_fb_info *fbi = &vid->jz_fb;
28.97 + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
28.98 +
28.99 + fbi->screen = (unsigned long)lcdbase;
28.100 + fbi->palette_size = 256;
28.101 + palette_mem_size = fbi->palette_size * sizeof(u16);
28.102 +
28.103 + /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */
28.104 + /* locate palette and descs at end of page following fb */
28.105 + fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
28.106 +
28.107 + return 0;
28.108 +}
28.109 +
28.110 +static void jz_lcd_desc_init(vidinfo_t *vid)
28.111 +{
28.112 + struct jz_fb_info * fbi;
28.113 + fbi = &vid->jz_fb;
28.114 + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
28.115 + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
28.116 + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
28.117 +
28.118 + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
28.119 +
28.120 + /* populate descriptors */
28.121 + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
28.122 + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
28.123 + fbi->dmadesc_fblow->fidr = 0;
28.124 + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
28.125 +
28.126 + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
28.127 +
28.128 + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
28.129 + fbi->dmadesc_fbhigh->fidr = 0;
28.130 + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
28.131 +
28.132 + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
28.133 + fbi->dmadesc_palette->fidr = 0;
28.134 + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
28.135 +
28.136 + if(NBITS(vid->vl_bpix) < 12)
28.137 + {
28.138 + /* assume any mode with <12 bpp is palette driven */
28.139 + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
28.140 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
28.141 + /* flips back and forth between pal and fbhigh */
28.142 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
28.143 + } else {
28.144 + /* palette shouldn't be loaded in true-color mode */
28.145 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
28.146 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
28.147 + }
28.148 +
28.149 + flush_cache_all();
28.150 +}
28.151 +
28.152 +static int jz_lcd_hw_init(vidinfo_t *vid)
28.153 +{
28.154 + struct jz_fb_info *fbi = &vid->jz_fb;
28.155 + unsigned int val = 0;
28.156 + unsigned int pclk;
28.157 + unsigned int stnH;
28.158 + int pll_div;
28.159 +
28.160 + /* Setting Control register */
28.161 + switch (jzfb.bpp) {
28.162 + case 1:
28.163 + val |= LCD_CTRL_BPP_1;
28.164 + break;
28.165 + case 2:
28.166 + val |= LCD_CTRL_BPP_2;
28.167 + break;
28.168 + case 4:
28.169 + val |= LCD_CTRL_BPP_4;
28.170 + break;
28.171 + case 8:
28.172 + val |= LCD_CTRL_BPP_8;
28.173 + break;
28.174 + case 15:
28.175 + val |= LCD_CTRL_RGB555;
28.176 + case 16:
28.177 + val |= LCD_CTRL_BPP_16;
28.178 + break;
28.179 + case 17 ... 32:
28.180 + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
28.181 + break;
28.182 +
28.183 + default:
28.184 + /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */
28.185 + val |= LCD_CTRL_BPP_16;
28.186 + break;
28.187 + }
28.188 +
28.189 + switch (jzfb.cfg & MODE_MASK) {
28.190 + case MODE_STN_MONO_DUAL:
28.191 + case MODE_STN_COLOR_DUAL:
28.192 + case MODE_STN_MONO_SINGLE:
28.193 + case MODE_STN_COLOR_SINGLE:
28.194 + switch (jzfb.bpp) {
28.195 + case 1:
28.196 + /* val |= LCD_CTRL_PEDN; */
28.197 + case 2:
28.198 + val |= LCD_CTRL_FRC_2;
28.199 + break;
28.200 + case 4:
28.201 + val |= LCD_CTRL_FRC_4;
28.202 + break;
28.203 + case 8:
28.204 + default:
28.205 + val |= LCD_CTRL_FRC_16;
28.206 + break;
28.207 + }
28.208 + break;
28.209 + }
28.210 +
28.211 + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
28.212 + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
28.213 +
28.214 + switch (jzfb.cfg & MODE_MASK) {
28.215 + case MODE_STN_MONO_DUAL:
28.216 + case MODE_STN_COLOR_DUAL:
28.217 + case MODE_STN_MONO_SINGLE:
28.218 + case MODE_STN_COLOR_SINGLE:
28.219 + switch (jzfb.cfg & STN_DAT_PINMASK) {
28.220 + case STN_DAT_PIN1:
28.221 + /* Do not adjust the hori-param value. */
28.222 + break;
28.223 + case STN_DAT_PIN2:
28.224 + align2(jzfb.hsw);
28.225 + align2(jzfb.elw);
28.226 + align2(jzfb.blw);
28.227 + break;
28.228 + case STN_DAT_PIN4:
28.229 + align4(jzfb.hsw);
28.230 + align4(jzfb.elw);
28.231 + align4(jzfb.blw);
28.232 + break;
28.233 + case STN_DAT_PIN8:
28.234 + align8(jzfb.hsw);
28.235 + align8(jzfb.elw);
28.236 + align8(jzfb.blw);
28.237 + break;
28.238 + }
28.239 + break;
28.240 + }
28.241 +
28.242 + REG_LCD_CTRL = val;
28.243 +
28.244 + switch (jzfb.cfg & MODE_MASK) {
28.245 + case MODE_STN_MONO_DUAL:
28.246 + case MODE_STN_COLOR_DUAL:
28.247 + case MODE_STN_MONO_SINGLE:
28.248 + case MODE_STN_COLOR_SINGLE:
28.249 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
28.250 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
28.251 + stnH = jzfb.h >> 1;
28.252 + else
28.253 + stnH = jzfb.h;
28.254 +
28.255 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
28.256 + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
28.257 +
28.258 + /* Screen setting */
28.259 + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
28.260 + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
28.261 + REG_LCD_DAV = (0 << 16) | (stnH);
28.262 +
28.263 + /* AC BIAs signal */
28.264 + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
28.265 +
28.266 + break;
28.267 +
28.268 + case MODE_TFT_GEN:
28.269 + case MODE_TFT_SHARP:
28.270 + case MODE_TFT_CASIO:
28.271 + case MODE_TFT_SAMSUNG:
28.272 + case MODE_8BIT_SERIAL_TFT:
28.273 + case MODE_TFT_18BIT:
28.274 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
28.275 + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
28.276 + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
28.277 + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
28.278 + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
28.279 + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
28.280 + break;
28.281 + }
28.282 +
28.283 + switch (jzfb.cfg & MODE_MASK) {
28.284 + case MODE_TFT_SAMSUNG:
28.285 + {
28.286 + unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
28.287 + unsigned int rev_s, rev_e, inv_s, inv_e;
28.288 +
28.289 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
28.290 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
28.291 +
28.292 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
28.293 + tp_s = jzfb.blw + jzfb.w + 1;
28.294 + tp_e = tp_s + 1;
28.295 + /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
28.296 + ckv_s = tp_s - pclk/(1000000000/4100);
28.297 + ckv_e = tp_s + total;
28.298 + rev_s = tp_s - 11; /* -11.5 clk */
28.299 + rev_e = rev_s + total;
28.300 + inv_s = tp_s;
28.301 + inv_e = inv_s + total;
28.302 + REG_LCD_CLS = (tp_s << 16) | tp_e;
28.303 + REG_LCD_PS = (ckv_s << 16) | ckv_e;
28.304 + REG_LCD_SPL = (rev_s << 16) | rev_e;
28.305 + REG_LCD_REV = (inv_s << 16) | inv_e;
28.306 + jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
28.307 + break;
28.308 + }
28.309 + case MODE_TFT_SHARP:
28.310 + {
28.311 + unsigned int total, cls_s, cls_e, ps_s, ps_e;
28.312 + unsigned int spl_s, spl_e, rev_s, rev_e;
28.313 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
28.314 + spl_s = 1;
28.315 + spl_e = spl_s + 1;
28.316 + cls_s = 0;
28.317 + cls_e = total - 60; /* > 4us (pclk = 80ns) */
28.318 + ps_s = cls_s;
28.319 + ps_e = cls_e;
28.320 + rev_s = total - 40; /* > 3us (pclk = 80ns) */
28.321 + rev_e = rev_s + total;
28.322 + jzfb.cfg |= STFT_PSHI;
28.323 + REG_LCD_SPL = (spl_s << 16) | spl_e;
28.324 + REG_LCD_CLS = (cls_s << 16) | cls_e;
28.325 + REG_LCD_PS = (ps_s << 16) | ps_e;
28.326 + REG_LCD_REV = (rev_s << 16) | rev_e;
28.327 + break;
28.328 + }
28.329 + case MODE_TFT_CASIO:
28.330 + break;
28.331 + }
28.332 +
28.333 + /* Configure the LCD panel */
28.334 + REG_LCD_CFG = jzfb.cfg;
28.335 +
28.336 + /* Timing setting */
28.337 + __cpm_stop_lcd();
28.338 +
28.339 + val = jzfb.fclk; /* frame clk */
28.340 + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
28.341 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
28.342 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
28.343 + } else {
28.344 + /* serial mode: Hsync period = 3*Width_Pixel */
28.345 + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
28.346 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
28.347 + }
28.348 +
28.349 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
28.350 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
28.351 + pclk = (pclk * 3);
28.352 +
28.353 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
28.354 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
28.355 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
28.356 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
28.357 + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
28.358 +
28.359 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
28.360 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
28.361 + pclk >>= 1;
28.362 +
28.363 + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
28.364 + pll_div = pll_div ? 1 : 2 ;
28.365 + val = ( __cpm_get_pllout()/pll_div ) / pclk;
28.366 + val--;
28.367 + if ( val > 0x1ff ) {
28.368 + /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */
28.369 + val = 0x1ff;
28.370 + }
28.371 + __cpm_set_pixdiv(val);
28.372 +
28.373 + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
28.374 + if ( val > 150000000 ) {
28.375 + /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */
28.376 + /* printf("Change LCDClock to 150MHz\n"); */
28.377 + val = 150000000;
28.378 + }
28.379 + val = ( __cpm_get_pllout()/pll_div ) / val;
28.380 + val--;
28.381 + if ( val > 0x1f ) {
28.382 + /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */
28.383 + val = 0x1f;
28.384 + }
28.385 + __cpm_set_ldiv( val );
28.386 + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
28.387 +
28.388 + __cpm_start_lcd();
28.389 + udelay(1000);
28.390 +
28.391 + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
28.392 +
28.393 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
28.394 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
28.395 + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
28.396 +
28.397 + return 0;
28.398 +}
28.399 +
28.400 +void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue)
28.401 +{
28.402 +}
28.403 +
28.404 +void lcd_initcolregs (void)
28.405 +{
28.406 +}
29.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
29.2 +++ b/stage2/nanonote_gpm940b0.h Sun Jun 07 23:06:08 2015 +0200
29.3 @@ -0,0 +1,143 @@
29.4 +/*
29.5 + * JzRISC lcd controller
29.6 + *
29.7 + * Xiangfu Liu <xiangfu@sharism.cc>
29.8 + *
29.9 + * This program is free software; you can redistribute it and/or
29.10 + * modify it under the terms of the GNU General Public License as
29.11 + * published by the Free Software Foundation; either version 2 of
29.12 + * the License, or (at your option) any later version.
29.13 + *
29.14 + * This program is distributed in the hope that it will be useful,
29.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
29.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29.17 + * GNU General Public License for more details.
29.18 + *
29.19 + * You should have received a copy of the GNU General Public License
29.20 + * along with this program; if not, write to the Free Software
29.21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29.22 + * MA 02111-1307 USA
29.23 + */
29.24 +
29.25 +#ifndef __QI_LB60_GPM940B0_H__
29.26 +#define __QI_LB60_GPM940B0_H__
29.27 +
29.28 +#include "nanonote.h"
29.29 +#include "jz4740_lcd.h"
29.30 +
29.31 +unsigned long lcd_get_size(void);
29.32 +void lcd_ctrl_init(void *lcdbase);
29.33 +void lcd_enable(void);
29.34 +void lcd_disable(void);
29.35 +
29.36 +struct lcd_desc{
29.37 + unsigned int next_desc; /* LCDDAx */
29.38 + unsigned int databuf; /* LCDSAx */
29.39 + unsigned int frame_id; /* LCDFIDx */
29.40 + unsigned int cmd; /* LCDCMDx */
29.41 +};
29.42 +
29.43 +#define MODE_MASK 0x0f
29.44 +#define MODE_TFT_GEN 0x00
29.45 +#define MODE_TFT_SHARP 0x01
29.46 +#define MODE_TFT_CASIO 0x02
29.47 +#define MODE_TFT_SAMSUNG 0x03
29.48 +#define MODE_CCIR656_NONINT 0x04
29.49 +#define MODE_CCIR656_INT 0x05
29.50 +#define MODE_STN_COLOR_SINGLE 0x08
29.51 +#define MODE_STN_MONO_SINGLE 0x09
29.52 +#define MODE_STN_COLOR_DUAL 0x0a
29.53 +#define MODE_STN_MONO_DUAL 0x0b
29.54 +#define MODE_8BIT_SERIAL_TFT 0x0c
29.55 +
29.56 +#define MODE_TFT_18BIT (1<<7)
29.57 +
29.58 +#define STN_DAT_PIN1 (0x00 << 4)
29.59 +#define STN_DAT_PIN2 (0x01 << 4)
29.60 +#define STN_DAT_PIN4 (0x02 << 4)
29.61 +#define STN_DAT_PIN8 (0x03 << 4)
29.62 +#define STN_DAT_PINMASK STN_DAT_PIN8
29.63 +
29.64 +#define STFT_PSHI (1 << 15)
29.65 +#define STFT_CLSHI (1 << 14)
29.66 +#define STFT_SPLHI (1 << 13)
29.67 +#define STFT_REVHI (1 << 12)
29.68 +
29.69 +#define SYNC_MASTER (0 << 16)
29.70 +#define SYNC_SLAVE (1 << 16)
29.71 +
29.72 +#define DE_P (0 << 9)
29.73 +#define DE_N (1 << 9)
29.74 +
29.75 +#define PCLK_P (0 << 10)
29.76 +#define PCLK_N (1 << 10)
29.77 +
29.78 +#define HSYNC_P (0 << 11)
29.79 +#define HSYNC_N (1 << 11)
29.80 +
29.81 +#define VSYNC_P (0 << 8)
29.82 +#define VSYNC_N (1 << 8)
29.83 +
29.84 +#define DATA_NORMAL (0 << 17)
29.85 +#define DATA_INVERSE (1 << 17)
29.86 +
29.87 +
29.88 +/* Jz LCDFB supported I/O controls. */
29.89 +#define FBIOSETBACKLIGHT 0x4688
29.90 +#define FBIODISPON 0x4689
29.91 +#define FBIODISPOFF 0x468a
29.92 +#define FBIORESET 0x468b
29.93 +#define FBIOPRINT_REG 0x468c
29.94 +
29.95 +/*
29.96 + * LCD panel specific definition
29.97 + */
29.98 +#define MODE (0xc9) /* 8bit serial RGB */
29.99 +
29.100 +#define __spi_write_reg1(reg, val) \
29.101 +do { \
29.102 + unsigned char no; \
29.103 + unsigned short value; \
29.104 + unsigned char a=reg; \
29.105 + unsigned char b=val; \
29.106 + __gpio_set_pin(SPEN); \
29.107 + __gpio_set_pin(SPCK); \
29.108 + __gpio_clear_pin(SPDA); \
29.109 + __gpio_clear_pin(SPEN); \
29.110 + value=((a<<8)|(b&0xFF)); \
29.111 + for(no=0;no<16;no++) \
29.112 + { \
29.113 + __gpio_clear_pin(SPCK); \
29.114 + if((value&0x8000)==0x8000) \
29.115 + __gpio_set_pin(SPDA); \
29.116 + else \
29.117 + __gpio_clear_pin(SPDA); \
29.118 + __gpio_set_pin(SPCK); \
29.119 + value=(value<<1); \
29.120 + } \
29.121 + __gpio_set_pin(SPEN); \
29.122 +} while (0)
29.123 +
29.124 +#define __lcd_display_pin_init() \
29.125 +do { \
29.126 + __cpm_start_tcu(); \
29.127 + __gpio_as_output(SPEN); /* use SPDA */ \
29.128 + __gpio_as_output(SPCK); /* use SPCK */ \
29.129 + __gpio_as_output(SPDA); /* use SPDA */ \
29.130 +} while (0)
29.131 +
29.132 +#define __lcd_display_on() \
29.133 +do { \
29.134 + __spi_write_reg1(0x05, 0x1e); \
29.135 + __spi_write_reg1(0x05, 0x5e); \
29.136 + __spi_write_reg1(0x07, 0x8d); \
29.137 + __spi_write_reg1(0x13, 0x01); \
29.138 + __spi_write_reg1(0x05, 0x5f); \
29.139 +} while (0)
29.140 +
29.141 +#define __lcd_display_off() \
29.142 +do { \
29.143 + __spi_write_reg1(0x05, 0x5e); \
29.144 +} while (0)
29.145 +
29.146 +#endif /* __QI_LB60_GPM940B0_H__ */
30.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
30.2 +++ b/stage2/stage2.c Sun Jun 07 23:06:08 2015 +0200
30.3 @@ -0,0 +1,62 @@
30.4 +/*
30.5 + * Ben NanoNote stage 2 payload test.
30.6 + *
30.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
30.8 + * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
30.9 + *
30.10 + * This program is free software; you can redistribute it and/or modify it under
30.11 + * the terms of the GNU General Public License as published by the Free Software
30.12 + * Foundation; either version 3 of the License, or (at your option) any later
30.13 + * version.
30.14 + *
30.15 + * This program is distributed in the hope that it will be useful, but WITHOUT
30.16 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
30.17 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
30.18 + * details.
30.19 + *
30.20 + * You should have received a copy of the GNU General Public License along with
30.21 + * this program. If not, see <http://www.gnu.org/licenses/>.
30.22 + */
30.23 +
30.24 +#include "board-nanonote.h"
30.25 +#include "lcd.h"
30.26 +
30.27 +void c_main(void)
30.28 +{
30.29 + /* Relocate object locations. */
30.30 +
30.31 + volatile unsigned int start_addr, got_start, got_end, addr, offset;
30.32 +
30.33 + /* get absolute start address */
30.34 + __asm__ __volatile__(
30.35 + "move %0, $20\n\t"
30.36 + : "=r"(start_addr)
30.37 + :
30.38 + );
30.39 +
30.40 + /* get related GOT address */
30.41 + __asm__ __volatile__(
30.42 + "la $4, _GLOBAL_OFFSET_TABLE_\n\t"
30.43 + "move %0, $4\n\t"
30.44 + "la $5, _got_end\n\t"
30.45 + "move %1, $5\n\t"
30.46 + : "=r"(got_start),"=r"(got_end)
30.47 + :
30.48 + );
30.49 +
30.50 + /* calculate offset and correct GOT*/
30.51 + offset = start_addr - 0x80000000;
30.52 + got_start += offset;
30.53 + got_end += offset;
30.54 +
30.55 + for ( addr = got_start + 8; addr < got_end; addr += 4 )
30.56 + *((volatile unsigned int *)(addr)) += offset; // add offset to correct all GOT
30.57 +
30.58 + /* The actual work. */
30.59 +
30.60 + gpio_init2();
30.61 + cpm_init();
30.62 + rtc_init();
30.63 + timer_init();
30.64 + lcd_init();
30.65 +}