1.1 --- a/include/nanonote.h Tue Jun 09 00:03:27 2015 +0200
1.2 +++ b/include/nanonote.h Tue Jun 09 21:10:40 2015 +0200
1.3 @@ -1,7 +1,7 @@
1.4 /*
1.5 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.6 * Copyright (C) 2009 Qi Hardware Inc.
1.7 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
1.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software; you can redistribute it and/or
1.11 * modify it under the terms of the GNU General Public License
1.12 @@ -33,44 +33,6 @@
1.13 #define LCD_BPP LCD_COLOR32
1.14
1.15 /*
1.16 - * RAM configuration
1.17 - */
1.18 -#define CONFIG_SYS_SDRAM_BASE 0x80000000
1.19 -
1.20 -/*
1.21 - * SDRAM configuration (timings in ns)
1.22 - */
1.23 -#define CONFIG_NR_DRAM_BANKS 1
1.24 -
1.25 -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1.26 -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1.27 -#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1.28 -#define SDRAM_COL 9 /* Column address: 8 to 12 */
1.29 -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1.30 -#define SDRAM_TRAS 45 /* RAS# Active Time */
1.31 -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1.32 -#define SDRAM_TPC 20 /* RAS# Precharge Time */
1.33 -#define SDRAM_TRWL 7 /* Write Latency Time */
1.34 -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1.35 -
1.36 -#define SDRAM_ROW0 11 /* Row address minimum */
1.37 -#define SDRAM_COL0 8 /* Column address minimum */
1.38 -#define SDRAM_BANK40 0 /* Bank minimum */
1.39 -
1.40 -/*
1.41 - * Cache configuration
1.42 - */
1.43 -#define CONFIG_SYS_DCACHE_SIZE 16384
1.44 -#define CONFIG_SYS_ICACHE_SIZE 16384
1.45 -#define CONFIG_SYS_CACHELINE_SIZE 32
1.46 -
1.47 -/*
1.48 - * Memory configuration
1.49 - */
1.50 -#define KSEG0 0x80000000
1.51 -#define PAGE_SIZE 4096
1.52 -
1.53 -/*
1.54 * GPIO definition
1.55 * See: http://en.qi-hardware.com/wiki/Hardware_basics
1.56 */
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
2.2 +++ b/include/sdram.h Tue Jun 09 21:10:40 2015 +0200
2.3 @@ -0,0 +1,68 @@
2.4 +/*
2.5 + * Common SDRAM configuration
2.6 + *
2.7 + * Copyright (C) 2009 Qi Hardware Inc.
2.8 + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
2.9 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
2.10 + *
2.11 + * This program is free software; you can redistribute it and/or
2.12 + * modify it under the terms of the GNU General Public License
2.13 + * as published by the Free Software Foundation; either version
2.14 + * 3 of the License, or (at your option) any later version.
2.15 + *
2.16 + * This program is distributed in the hope that it will be useful,
2.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2.19 + * GNU General Public License for more details.
2.20 + *
2.21 + * You should have received a copy of the GNU General Public License
2.22 + * along with this program; if not, write to the Free Software
2.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
2.24 + * Boston, MA 02110-1301, USA
2.25 + */
2.26 +
2.27 +#ifndef __SDRAM_H__
2.28 +#define __SDRAM_H__
2.29 +
2.30 +/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h
2.31 + via u-boot/arch/mips/include/asm/io.h */
2.32 +/* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */
2.33 +#define virt_to_phys(n) ((int) n)
2.34 +
2.35 +/*
2.36 + * RAM configuration
2.37 + */
2.38 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
2.39 +
2.40 +/*
2.41 + * SDRAM configuration (timings in ns)
2.42 + */
2.43 +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
2.44 +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
2.45 +#define SDRAM_ROW 13 /* Row address: 11 to 13 */
2.46 +#define SDRAM_COL 9 /* Column address: 8 to 12 */
2.47 +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
2.48 +#define SDRAM_TRAS 45 /* RAS# Active Time */
2.49 +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
2.50 +#define SDRAM_TPC 20 /* RAS# Precharge Time */
2.51 +#define SDRAM_TRWL 7 /* Write Latency Time */
2.52 +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
2.53 +
2.54 +#define SDRAM_ROW0 11 /* Row address minimum */
2.55 +#define SDRAM_COL0 8 /* Column address minimum */
2.56 +#define SDRAM_BANK40 0 /* Bank minimum */
2.57 +
2.58 +/*
2.59 + * Cache configuration
2.60 + */
2.61 +#define CONFIG_SYS_DCACHE_SIZE 16384
2.62 +#define CONFIG_SYS_ICACHE_SIZE 16384
2.63 +#define CONFIG_SYS_CACHELINE_SIZE 32
2.64 +
2.65 +/*
2.66 + * Memory configuration
2.67 + */
2.68 +#define KSEG0 0x80000000
2.69 +#define PAGE_SIZE 4096
2.70 +
2.71 +#endif /* __SDRAM_H__ */
3.1 --- a/stage1/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200
3.2 +++ b/stage1/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200
3.3 @@ -3,7 +3,7 @@
3.4 *
3.5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
3.6 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
3.7 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
3.8 + * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
3.9 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
3.10 *
3.11 * This program is free software; you can redistribute it and/or modify it under
3.12 @@ -21,7 +21,7 @@
3.13 */
3.14
3.15 #include "jz4740.h"
3.16 -#include "nanonote.h"
3.17 +#include "sdram.h"
3.18 #include "usb_boot_defines.h"
3.19
3.20 /* These arguments are initialised by usbboot and are defined in...
3.21 @@ -82,16 +82,19 @@
3.22 (2 << CPM_CPCCR_MDIV_BIT) |
3.23 (2 << CPM_CPCCR_LDIV_BIT);
3.24
3.25 - /* Determine the divider clock output based on the PCS bit. */
3.26 -
3.27 - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
3.28 -
3.29 /* Init USB Host clock.
3.30 - * Divisor == UHCCDR + 1
3.31 * Desired frequency == 48MHz
3.32 */
3.33
3.34 +#ifdef CONFIG_CPU_JZ4730
3.35 + cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25);
3.36 +#else
3.37 + /* Determine the divider clock output based on the PCS bit. */
3.38 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
3.39 +
3.40 + /* Divisor == UHCCDR + 1 */
3.41 REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
3.42 +#endif
3.43
3.44 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
3.45 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
3.46 @@ -172,10 +175,23 @@
3.47 EMC_SDMR_BL_4 |
3.48 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
3.49
3.50 + /* jz4730 additional measures */
3.51 +#ifdef CONFIG_CPU_JZ4730
3.52 + if (FW_SDRAM_BW16)
3.53 + sdmode <<= 1;
3.54 + else
3.55 + sdmode <<= 2;
3.56 +#endif
3.57 +
3.58 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
3.59 REG_EMC_DMCR = dmcr;
3.60 REG8(EMC_SDMR0|sdmode) = 0;
3.61
3.62 + /* jz4730 additional measures */
3.63 +#ifdef CONFIG_CPU_JZ4730
3.64 + REG8(EMC_SDMR1|sdmode) = 0;
3.65 +#endif
3.66 +
3.67 /* Wait for precharge, > 200us */
3.68 tmp = (cpu_clk / 1000000) * 1000;
3.69 while (tmp--);
3.70 @@ -198,6 +214,11 @@
3.71 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
3.72 REG8(EMC_SDMR0|sdmode) = 0;
3.73
3.74 + /* jz4730 additional measures */
3.75 +#ifdef CONFIG_CPU_JZ4730
3.76 + REG8(EMC_SDMR1|sdmode) = 0;
3.77 +#endif
3.78 +
3.79 /* Set back to basic DMCR value */
3.80 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
3.81
4.1 --- a/stage2/Makefile Tue Jun 09 00:03:27 2015 +0200
4.2 +++ b/stage2/Makefile Tue Jun 09 21:10:40 2015 +0200
4.3 @@ -42,8 +42,8 @@
4.4
4.5 # Ordering of objects is important and cannot be left to replacement rules.
4.6
4.7 -SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c
4.8 -OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o
4.9 +SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c jzlcd.c board.c
4.10 +OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o jzlcd.o board.o
4.11
4.12 .PHONY: all clean distclean
4.13
5.1 --- a/stage2/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200
5.2 +++ b/stage2/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200
5.3 @@ -1,10 +1,10 @@
5.4 /*
5.5 * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools.
5.6 *
5.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
5.8 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5.9 + * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
5.10 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
5.11 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
5.12 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5.13 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
5.14 *
5.15 * This program is free software; you can redistribute it and/or modify it under
5.16 * the terms of the GNU General Public License as published by the Free Software
5.17 @@ -20,7 +20,7 @@
5.18 * this program. If not, see <http://www.gnu.org/licenses/>.
5.19 */
5.20
5.21 -#include "jz4740.h"
5.22 +#include "board.h"
5.23 #include "nanonote.h"
5.24
5.25 /* Later initialisation functions. */
5.26 @@ -106,37 +106,10 @@
5.27 REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
5.28 }
5.29
5.30 -unsigned long get_memory_size(void)
5.31 -{
5.32 - unsigned int dmcr;
5.33 - unsigned int rows, cols, dw, banks;
5.34 - unsigned long size;
5.35 -
5.36 - dmcr = REG_EMC_DMCR;
5.37 - rows = SDRAM_ROW0 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
5.38 - cols = SDRAM_COL0 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
5.39 - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
5.40 - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
5.41 -
5.42 - size = (1 << (rows + cols)) * dw * banks;
5.43 -
5.44 - return size;
5.45 -}
5.46 -
5.47 /* Timer routines. */
5.48
5.49 -#define TIMER_CHAN 0
5.50 -#define TIMER_FDATA 0xffff /* Timer full data value */
5.51 -#define TIMER_HZ CONFIG_SYS_HZ
5.52 -
5.53 -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
5.54 -
5.55 -static unsigned long timestamp;
5.56 -static unsigned long lastdec;
5.57 -
5.58 -void reset_timer_masked(void);
5.59 -unsigned long get_timer_masked(void);
5.60 -void udelay_masked(unsigned long usec);
5.61 +unsigned long timestamp;
5.62 +unsigned long lastdec;
5.63
5.64 /*
5.65 * timer without interrupts
5.66 @@ -158,176 +131,3 @@
5.67
5.68 return 0;
5.69 }
5.70 -
5.71 -void reset_timer(void)
5.72 -{
5.73 - reset_timer_masked ();
5.74 -}
5.75 -
5.76 -unsigned long get_timer(unsigned long base)
5.77 -{
5.78 - return get_timer_masked () - base;
5.79 -}
5.80 -
5.81 -void set_timer(unsigned long t)
5.82 -{
5.83 - timestamp = t;
5.84 -}
5.85 -
5.86 -void udelay (unsigned long usec)
5.87 -{
5.88 - unsigned long tmo,tmp;
5.89 -
5.90 - /* normalize */
5.91 - if (usec >= 1000) {
5.92 - tmo = usec / 1000;
5.93 - tmo *= TIMER_HZ;
5.94 - tmo /= 1000;
5.95 - }
5.96 - else {
5.97 - if (usec >= 1) {
5.98 - tmo = usec * TIMER_HZ;
5.99 - tmo /= (1000*1000);
5.100 - }
5.101 - else
5.102 - tmo = 1;
5.103 - }
5.104 -
5.105 - /* check for rollover during this delay */
5.106 - tmp = get_timer (0);
5.107 - if ((tmp + tmo) < tmp )
5.108 - reset_timer_masked(); /* timer would roll over */
5.109 - else
5.110 - tmo += tmp;
5.111 -
5.112 - while (get_timer_masked () < tmo);
5.113 -}
5.114 -
5.115 -void reset_timer_masked (void)
5.116 -{
5.117 - /* reset time */
5.118 - lastdec = READ_TIMER;
5.119 - timestamp = 0;
5.120 -}
5.121 -
5.122 -unsigned long get_timer_masked (void)
5.123 -{
5.124 - unsigned long now = READ_TIMER;
5.125 -
5.126 - if (lastdec <= now) {
5.127 - /* normal mode */
5.128 - timestamp += (now - lastdec);
5.129 - } else {
5.130 - /* we have an overflow ... */
5.131 - timestamp += TIMER_FDATA + now - lastdec;
5.132 - }
5.133 - lastdec = now;
5.134 -
5.135 - return timestamp;
5.136 -}
5.137 -
5.138 -void udelay_masked (unsigned long usec)
5.139 -{
5.140 - unsigned long tmo;
5.141 - unsigned long endtime;
5.142 - signed long diff;
5.143 -
5.144 - /* normalize */
5.145 - if (usec >= 1000) {
5.146 - tmo = usec / 1000;
5.147 - tmo *= TIMER_HZ;
5.148 - tmo /= 1000;
5.149 - } else {
5.150 - if (usec > 1) {
5.151 - tmo = usec * TIMER_HZ;
5.152 - tmo /= (1000*1000);
5.153 - } else {
5.154 - tmo = 1;
5.155 - }
5.156 - }
5.157 -
5.158 - endtime = get_timer_masked () + tmo;
5.159 -
5.160 - do {
5.161 - unsigned long now = get_timer_masked ();
5.162 - diff = endtime - now;
5.163 - } while (diff >= 0);
5.164 -}
5.165 -
5.166 -/*
5.167 - * This function is derived from PowerPC code (read timebase as long long).
5.168 - * On MIPS it just returns the timer value.
5.169 - */
5.170 -unsigned long long get_ticks(void)
5.171 -{
5.172 - return get_timer(0);
5.173 -}
5.174 -
5.175 -/*
5.176 - * This function is derived from PowerPC code (timebase clock frequency).
5.177 - * On MIPS it returns the number of timer ticks per second.
5.178 - */
5.179 -unsigned long get_tbclk (void)
5.180 -{
5.181 - return TIMER_HZ;
5.182 -}
5.183 -
5.184 -/* CPU-specific routines from U-Boot.
5.185 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
5.186 - See: u-boot/arch/mips/include/asm/cacheops.h
5.187 -*/
5.188 -
5.189 -#define Index_Store_Tag_I 0x08
5.190 -#define Index_Writeback_Inv_D 0x15
5.191 -
5.192 -void flush_icache_all(void)
5.193 -{
5.194 - u32 addr, t = 0;
5.195 -
5.196 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
5.197 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
5.198 -
5.199 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
5.200 - addr += CONFIG_SYS_CACHELINE_SIZE) {
5.201 - asm volatile (
5.202 - ".set mips3\n\t"
5.203 - " cache %0, 0(%1)\n\t"
5.204 - ".set mips2\n\t"
5.205 - :
5.206 - : "I" (Index_Store_Tag_I), "r"(addr));
5.207 - }
5.208 -
5.209 - /* invalicate btb */
5.210 - asm volatile (
5.211 - ".set mips32\n\t"
5.212 - "mfc0 %0, $16, 7\n\t"
5.213 - "nop\n\t"
5.214 - "ori %0,2\n\t"
5.215 - "mtc0 %0, $16, 7\n\t"
5.216 - ".set mips2\n\t"
5.217 - :
5.218 - : "r" (t));
5.219 -}
5.220 -
5.221 -void flush_dcache_all(void)
5.222 -{
5.223 - u32 addr;
5.224 -
5.225 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
5.226 - addr += CONFIG_SYS_CACHELINE_SIZE) {
5.227 - asm volatile (
5.228 - ".set mips3\n\t"
5.229 - " cache %0, 0(%1)\n\t"
5.230 - ".set mips2\n\t"
5.231 - :
5.232 - : "I" (Index_Writeback_Inv_D), "r"(addr));
5.233 - }
5.234 -
5.235 - asm volatile ("sync");
5.236 -}
5.237 -
5.238 -void flush_cache_all(void)
5.239 -{
5.240 - flush_dcache_all();
5.241 - flush_icache_all();
5.242 -}
6.1 --- a/stage2/board-nanonote.h Tue Jun 09 00:03:27 2015 +0200
6.2 +++ b/stage2/board-nanonote.h Tue Jun 09 21:10:40 2015 +0200
6.3 @@ -1,5 +1,5 @@
6.4 -#ifndef __BOARD_NANONOTE2_H__
6.5 -#define __BOARD_NANONOTE2_H__
6.6 +#ifndef __BOARD_NANONOTE_H__
6.7 +#define __BOARD_NANONOTE_H__
6.8
6.9 /* Initialisation functions. */
6.10
6.11 @@ -8,10 +8,4 @@
6.12 void rtc_init(void);
6.13 int timer_init(void);
6.14
6.15 -/* Utility functions. */
6.16 -
6.17 -void udelay(unsigned long usec);
6.18 -void flush_cache_all(void);
6.19 -unsigned long get_memory_size(void);
6.20 -
6.21 -#endif /* __BOARD_NANONOTE2_H__ */
6.22 +#endif /* __BOARD_NANONOTE_H__ */
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/stage2/board.c Tue Jun 09 21:10:40 2015 +0200
7.3 @@ -0,0 +1,219 @@
7.4 +/*
7.5 + * Common routines supporting board initialisation.
7.6 + *
7.7 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
7.8 + * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
7.9 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
7.10 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
7.11 + *
7.12 + * This program is free software; you can redistribute it and/or modify it under
7.13 + * the terms of the GNU General Public License as published by the Free Software
7.14 + * Foundation; either version 3 of the License, or (at your option) any later
7.15 + * version.
7.16 + *
7.17 + * This program is distributed in the hope that it will be useful, but WITHOUT
7.18 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
7.19 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
7.20 + * details.
7.21 + *
7.22 + * You should have received a copy of the GNU General Public License along with
7.23 + * this program. If not, see <http://www.gnu.org/licenses/>.
7.24 + */
7.25 +
7.26 +#include "sdram.h"
7.27 +#include "board.h"
7.28 +
7.29 +unsigned long get_memory_size(void)
7.30 +{
7.31 + unsigned int dmcr;
7.32 + unsigned int rows, cols, dw, banks;
7.33 + unsigned long size;
7.34 +
7.35 + dmcr = REG_EMC_DMCR;
7.36 + rows = SDRAM_ROW0 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
7.37 + cols = SDRAM_COL0 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
7.38 + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
7.39 + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
7.40 +
7.41 + size = (1 << (rows + cols)) * dw * banks;
7.42 +
7.43 + return size;
7.44 +}
7.45 +
7.46 +/* Timer routines. */
7.47 +
7.48 +extern unsigned long timestamp;
7.49 +extern unsigned long lastdec;
7.50 +
7.51 +unsigned long get_timer_masked (void)
7.52 +{
7.53 + unsigned long now = READ_TIMER;
7.54 +
7.55 + if (lastdec <= now) {
7.56 + /* normal mode */
7.57 + timestamp += (now - lastdec);
7.58 + } else {
7.59 + /* we have an overflow ... */
7.60 + timestamp += TIMER_FDATA + now - lastdec;
7.61 + }
7.62 + lastdec = now;
7.63 +
7.64 + return timestamp;
7.65 +}
7.66 +
7.67 +void reset_timer_masked (void)
7.68 +{
7.69 + /* reset time */
7.70 + lastdec = READ_TIMER;
7.71 + timestamp = 0;
7.72 +}
7.73 +
7.74 +void reset_timer(void)
7.75 +{
7.76 + reset_timer_masked ();
7.77 +}
7.78 +
7.79 +unsigned long get_timer(unsigned long base)
7.80 +{
7.81 + return get_timer_masked () - base;
7.82 +}
7.83 +
7.84 +void set_timer(unsigned long t)
7.85 +{
7.86 + timestamp = t;
7.87 +}
7.88 +
7.89 +void udelay (unsigned long usec)
7.90 +{
7.91 + unsigned long tmo,tmp;
7.92 +
7.93 + /* normalize */
7.94 + if (usec >= 1000) {
7.95 + tmo = usec / 1000;
7.96 + tmo *= TIMER_HZ;
7.97 + tmo /= 1000;
7.98 + }
7.99 + else {
7.100 + if (usec >= 1) {
7.101 + tmo = usec * TIMER_HZ;
7.102 + tmo /= (1000*1000);
7.103 + }
7.104 + else
7.105 + tmo = 1;
7.106 + }
7.107 +
7.108 + /* check for rollover during this delay */
7.109 + tmp = get_timer (0);
7.110 + if ((tmp + tmo) < tmp )
7.111 + reset_timer_masked(); /* timer would roll over */
7.112 + else
7.113 + tmo += tmp;
7.114 +
7.115 + while (get_timer_masked () < tmo);
7.116 +}
7.117 +
7.118 +void udelay_masked (unsigned long usec)
7.119 +{
7.120 + unsigned long tmo;
7.121 + unsigned long endtime;
7.122 + signed long diff;
7.123 +
7.124 + /* normalize */
7.125 + if (usec >= 1000) {
7.126 + tmo = usec / 1000;
7.127 + tmo *= TIMER_HZ;
7.128 + tmo /= 1000;
7.129 + } else {
7.130 + if (usec > 1) {
7.131 + tmo = usec * TIMER_HZ;
7.132 + tmo /= (1000*1000);
7.133 + } else {
7.134 + tmo = 1;
7.135 + }
7.136 + }
7.137 +
7.138 + endtime = get_timer_masked () + tmo;
7.139 +
7.140 + do {
7.141 + unsigned long now = get_timer_masked ();
7.142 + diff = endtime - now;
7.143 + } while (diff >= 0);
7.144 +}
7.145 +
7.146 +/*
7.147 + * This function is derived from PowerPC code (read timebase as long long).
7.148 + * On MIPS it just returns the timer value.
7.149 + */
7.150 +unsigned long long get_ticks(void)
7.151 +{
7.152 + return get_timer(0);
7.153 +}
7.154 +
7.155 +/*
7.156 + * This function is derived from PowerPC code (timebase clock frequency).
7.157 + * On MIPS it returns the number of timer ticks per second.
7.158 + */
7.159 +unsigned long get_tbclk (void)
7.160 +{
7.161 + return TIMER_HZ;
7.162 +}
7.163 +
7.164 +/* CPU-specific routines from U-Boot.
7.165 + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
7.166 + See: u-boot/arch/mips/include/asm/cacheops.h
7.167 +*/
7.168 +
7.169 +#define Index_Store_Tag_I 0x08
7.170 +#define Index_Writeback_Inv_D 0x15
7.171 +
7.172 +void flush_icache_all(void)
7.173 +{
7.174 + u32 addr, t = 0;
7.175 +
7.176 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
7.177 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
7.178 +
7.179 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
7.180 + addr += CONFIG_SYS_CACHELINE_SIZE) {
7.181 + asm volatile (
7.182 + ".set mips3\n\t"
7.183 + " cache %0, 0(%1)\n\t"
7.184 + ".set mips2\n\t"
7.185 + :
7.186 + : "I" (Index_Store_Tag_I), "r"(addr));
7.187 + }
7.188 +
7.189 + /* invalicate btb */
7.190 + asm volatile (
7.191 + ".set mips32\n\t"
7.192 + "mfc0 %0, $16, 7\n\t"
7.193 + "nop\n\t"
7.194 + "ori %0,2\n\t"
7.195 + "mtc0 %0, $16, 7\n\t"
7.196 + ".set mips2\n\t"
7.197 + :
7.198 + : "r" (t));
7.199 +}
7.200 +
7.201 +void flush_dcache_all(void)
7.202 +{
7.203 + u32 addr;
7.204 +
7.205 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
7.206 + addr += CONFIG_SYS_CACHELINE_SIZE) {
7.207 + asm volatile (
7.208 + ".set mips3\n\t"
7.209 + " cache %0, 0(%1)\n\t"
7.210 + ".set mips2\n\t"
7.211 + :
7.212 + : "I" (Index_Writeback_Inv_D), "r"(addr));
7.213 + }
7.214 +
7.215 + asm volatile ("sync");
7.216 +}
7.217 +
7.218 +void flush_cache_all(void)
7.219 +{
7.220 + flush_dcache_all();
7.221 + flush_icache_all();
7.222 +}
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/stage2/board.h Tue Jun 09 21:10:40 2015 +0200
8.3 @@ -0,0 +1,23 @@
8.4 +#ifndef __BOARD_H__
8.5 +#define __BOARD_H__
8.6 +
8.7 +/* Utility functions. */
8.8 +
8.9 +void udelay(unsigned long usec);
8.10 +void flush_cache_all(void);
8.11 +unsigned long get_memory_size(void);
8.12 +
8.13 +#ifdef CONFIG_CPU_JZ4730
8.14 +#include "jz4730.h"
8.15 +#define READ_TIMER __ost_get_count(TIMER_CHAN) /* macro to read the 32 bit timer */
8.16 +#define TIMER_FDATA 0xffffffff /* timer full data value */
8.17 +#else
8.18 +#include "jz4740.h"
8.19 +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
8.20 +#define TIMER_FDATA 0xffff /* timer full data value */
8.21 +#endif
8.22 +
8.23 +#define TIMER_HZ CONFIG_SYS_HZ
8.24 +#define TIMER_CHAN 0
8.25 +
8.26 +#endif /* __BOARD_H__ */
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/stage2/jzlcd.c Tue Jun 09 21:10:40 2015 +0200
9.3 @@ -0,0 +1,389 @@
9.4 +/*
9.5 + * JzRISC lcd controller
9.6 + *
9.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
9.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
9.9 + *
9.10 + * This program is free software; you can redistribute it and/or
9.11 + * modify it under the terms of the GNU General Public License as
9.12 + * published by the Free Software Foundation; either version 2 of
9.13 + * the License, or (at your option) any later version.
9.14 + *
9.15 + * This program is distributed in the hope that it will be useful,
9.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9.18 + * GNU General Public License for more details.
9.19 + *
9.20 + * You should have received a copy of the GNU General Public License
9.21 + * along with this program; if not, write to the Free Software
9.22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9.23 + * MA 02111-1307 USA
9.24 + */
9.25 +
9.26 +#include "nanonote_gpm940b0.h"
9.27 +#include "sdram.h"
9.28 +#include "jzlcd.h"
9.29 +#include "board.h"
9.30 +
9.31 +#define align2(n) (n)=((((n)+1)>>1)<<1)
9.32 +#define align4(n) (n)=((((n)+3)>>2)<<2)
9.33 +#define align8(n) (n)=((((n)+7)>>3)<<3)
9.34 +
9.35 +extern struct jzfb_info jzfb;
9.36 +
9.37 +unsigned long lcd_get_size(void)
9.38 +{
9.39 + int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
9.40 + return line_length * panel_info.vl_row;
9.41 +}
9.42 +
9.43 +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
9.44 +static void jz_lcd_desc_init(vidinfo_t *vid);
9.45 +static int jz_lcd_hw_init(vidinfo_t *vid);
9.46 +
9.47 +void lcd_ctrl_init (void *lcdbase)
9.48 +{
9.49 + jz_lcd_init_mem(lcdbase, &panel_info);
9.50 + jz_lcd_desc_init(&panel_info);
9.51 + jz_lcd_hw_init(&panel_info);
9.52 +}
9.53 +
9.54 +/*
9.55 + * Before enabled lcd controller, lcd registers should be configured correctly.
9.56 + */
9.57 +void lcd_enable (void)
9.58 +{
9.59 + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
9.60 + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
9.61 +}
9.62 +
9.63 +void lcd_disable (void)
9.64 +{
9.65 + REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
9.66 + /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
9.67 +}
9.68 +
9.69 +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
9.70 +{
9.71 + unsigned long palette_mem_size;
9.72 + struct jz_fb_info *fbi = &vid->jz_fb;
9.73 + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
9.74 +
9.75 + fbi->screen = (unsigned long)lcdbase;
9.76 + fbi->palette_size = 256;
9.77 + palette_mem_size = fbi->palette_size * sizeof(u16);
9.78 +
9.79 + /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */
9.80 + /* locate palette and descs at end of page following fb */
9.81 + fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
9.82 +
9.83 + return 0;
9.84 +}
9.85 +
9.86 +static void jz_lcd_desc_init(vidinfo_t *vid)
9.87 +{
9.88 + struct jz_fb_info * fbi;
9.89 + fbi = &vid->jz_fb;
9.90 + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
9.91 + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
9.92 + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
9.93 +
9.94 + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
9.95 +
9.96 + /* populate descriptors */
9.97 + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
9.98 + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
9.99 + fbi->dmadesc_fblow->fidr = 0;
9.100 + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
9.101 +
9.102 + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
9.103 +
9.104 + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
9.105 + fbi->dmadesc_fbhigh->fidr = 0;
9.106 + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
9.107 +
9.108 + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
9.109 + fbi->dmadesc_palette->fidr = 0;
9.110 + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
9.111 +
9.112 + if(NBITS(vid->vl_bpix) < 12)
9.113 + {
9.114 + /* assume any mode with <12 bpp is palette driven */
9.115 + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
9.116 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
9.117 + /* flips back and forth between pal and fbhigh */
9.118 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
9.119 + } else {
9.120 + /* palette shouldn't be loaded in true-color mode */
9.121 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
9.122 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
9.123 + }
9.124 +
9.125 + flush_cache_all();
9.126 +}
9.127 +
9.128 +static int jz_lcd_hw_init(vidinfo_t *vid)
9.129 +{
9.130 + struct jz_fb_info *fbi = &vid->jz_fb;
9.131 + unsigned int val = 0;
9.132 + unsigned int pclk;
9.133 + unsigned int stnH;
9.134 + int pll_div;
9.135 +
9.136 + /* Setting Control register */
9.137 + switch (jzfb.bpp) {
9.138 + case 1:
9.139 + val |= LCD_CTRL_BPP_1;
9.140 + break;
9.141 + case 2:
9.142 + val |= LCD_CTRL_BPP_2;
9.143 + break;
9.144 + case 4:
9.145 + val |= LCD_CTRL_BPP_4;
9.146 + break;
9.147 + case 8:
9.148 + val |= LCD_CTRL_BPP_8;
9.149 + break;
9.150 + case 15:
9.151 + val |= LCD_CTRL_RGB555;
9.152 + case 16:
9.153 + val |= LCD_CTRL_BPP_16;
9.154 + break;
9.155 + case 17 ... 32:
9.156 + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
9.157 + break;
9.158 +
9.159 + default:
9.160 + /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */
9.161 + val |= LCD_CTRL_BPP_16;
9.162 + break;
9.163 + }
9.164 +
9.165 + switch (jzfb.cfg & MODE_MASK) {
9.166 + case MODE_STN_MONO_DUAL:
9.167 + case MODE_STN_COLOR_DUAL:
9.168 + case MODE_STN_MONO_SINGLE:
9.169 + case MODE_STN_COLOR_SINGLE:
9.170 + switch (jzfb.bpp) {
9.171 + case 1:
9.172 + /* val |= LCD_CTRL_PEDN; */
9.173 + case 2:
9.174 + val |= LCD_CTRL_FRC_2;
9.175 + break;
9.176 + case 4:
9.177 + val |= LCD_CTRL_FRC_4;
9.178 + break;
9.179 + case 8:
9.180 + default:
9.181 + val |= LCD_CTRL_FRC_16;
9.182 + break;
9.183 + }
9.184 + break;
9.185 + }
9.186 +
9.187 + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
9.188 + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
9.189 +
9.190 + switch (jzfb.cfg & MODE_MASK) {
9.191 + case MODE_STN_MONO_DUAL:
9.192 + case MODE_STN_COLOR_DUAL:
9.193 + case MODE_STN_MONO_SINGLE:
9.194 + case MODE_STN_COLOR_SINGLE:
9.195 + switch (jzfb.cfg & STN_DAT_PINMASK) {
9.196 + case STN_DAT_PIN1:
9.197 + /* Do not adjust the hori-param value. */
9.198 + break;
9.199 + case STN_DAT_PIN2:
9.200 + align2(jzfb.hsw);
9.201 + align2(jzfb.elw);
9.202 + align2(jzfb.blw);
9.203 + break;
9.204 + case STN_DAT_PIN4:
9.205 + align4(jzfb.hsw);
9.206 + align4(jzfb.elw);
9.207 + align4(jzfb.blw);
9.208 + break;
9.209 + case STN_DAT_PIN8:
9.210 + align8(jzfb.hsw);
9.211 + align8(jzfb.elw);
9.212 + align8(jzfb.blw);
9.213 + break;
9.214 + }
9.215 + break;
9.216 + }
9.217 +
9.218 + REG_LCD_CTRL = val;
9.219 +
9.220 + switch (jzfb.cfg & MODE_MASK) {
9.221 + case MODE_STN_MONO_DUAL:
9.222 + case MODE_STN_COLOR_DUAL:
9.223 + case MODE_STN_MONO_SINGLE:
9.224 + case MODE_STN_COLOR_SINGLE:
9.225 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
9.226 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
9.227 + stnH = jzfb.h >> 1;
9.228 + else
9.229 + stnH = jzfb.h;
9.230 +
9.231 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
9.232 + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
9.233 +
9.234 + /* Screen setting */
9.235 + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
9.236 + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
9.237 + REG_LCD_DAV = (0 << 16) | (stnH);
9.238 +
9.239 + /* AC BIAs signal */
9.240 + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
9.241 +
9.242 + break;
9.243 +
9.244 + case MODE_TFT_GEN:
9.245 + case MODE_TFT_SHARP:
9.246 + case MODE_TFT_CASIO:
9.247 + case MODE_TFT_SAMSUNG:
9.248 + case MODE_8BIT_SERIAL_TFT:
9.249 + case MODE_TFT_18BIT:
9.250 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
9.251 + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
9.252 + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
9.253 + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
9.254 + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
9.255 + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
9.256 + break;
9.257 + }
9.258 +
9.259 + switch (jzfb.cfg & MODE_MASK) {
9.260 + case MODE_TFT_SAMSUNG:
9.261 + {
9.262 + unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
9.263 + unsigned int rev_s, rev_e, inv_s, inv_e;
9.264 +
9.265 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
9.266 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
9.267 +
9.268 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
9.269 + tp_s = jzfb.blw + jzfb.w + 1;
9.270 + tp_e = tp_s + 1;
9.271 + /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
9.272 + ckv_s = tp_s - pclk/(1000000000/4100);
9.273 + ckv_e = tp_s + total;
9.274 + rev_s = tp_s - 11; /* -11.5 clk */
9.275 + rev_e = rev_s + total;
9.276 + inv_s = tp_s;
9.277 + inv_e = inv_s + total;
9.278 + REG_LCD_CLS = (tp_s << 16) | tp_e;
9.279 + REG_LCD_PS = (ckv_s << 16) | ckv_e;
9.280 + REG_LCD_SPL = (rev_s << 16) | rev_e;
9.281 + REG_LCD_REV = (inv_s << 16) | inv_e;
9.282 + jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
9.283 + break;
9.284 + }
9.285 + case MODE_TFT_SHARP:
9.286 + {
9.287 + unsigned int total, cls_s, cls_e, ps_s, ps_e;
9.288 + unsigned int spl_s, spl_e, rev_s, rev_e;
9.289 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
9.290 + spl_s = 1;
9.291 + spl_e = spl_s + 1;
9.292 + cls_s = 0;
9.293 + cls_e = total - 60; /* > 4us (pclk = 80ns) */
9.294 + ps_s = cls_s;
9.295 + ps_e = cls_e;
9.296 + rev_s = total - 40; /* > 3us (pclk = 80ns) */
9.297 + rev_e = rev_s + total;
9.298 + jzfb.cfg |= STFT_PSHI;
9.299 + REG_LCD_SPL = (spl_s << 16) | spl_e;
9.300 + REG_LCD_CLS = (cls_s << 16) | cls_e;
9.301 + REG_LCD_PS = (ps_s << 16) | ps_e;
9.302 + REG_LCD_REV = (rev_s << 16) | rev_e;
9.303 + break;
9.304 + }
9.305 + case MODE_TFT_CASIO:
9.306 + break;
9.307 + }
9.308 +
9.309 + /* Configure the LCD panel */
9.310 + REG_LCD_CFG = jzfb.cfg;
9.311 +
9.312 + /* Timing setting */
9.313 + __cpm_stop_lcd();
9.314 +
9.315 + val = jzfb.fclk; /* frame clk */
9.316 + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
9.317 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
9.318 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
9.319 + } else {
9.320 + /* serial mode: Hsync period = 3*Width_Pixel */
9.321 + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
9.322 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
9.323 + }
9.324 +
9.325 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
9.326 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
9.327 + pclk = (pclk * 3);
9.328 +
9.329 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
9.330 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
9.331 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
9.332 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
9.333 + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
9.334 +
9.335 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
9.336 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
9.337 + pclk >>= 1;
9.338 +
9.339 +#ifdef CONFIG_CPU_JZ4730
9.340 + val = __cpm_get_pllout() / pclk;
9.341 + REG_CPM_CFCR2 = val - 1;
9.342 + val = pclk * 4 ;
9.343 + if ( val > 150000000 ) {
9.344 + val = 150000000;
9.345 + }
9.346 + val = __cpm_get_pllout() / val;
9.347 + val--;
9.348 + if ( val > 0xF )
9.349 + val = 0xF;
9.350 + __cpm_set_lcdclk_div(val);
9.351 + REG_CPM_CFCR |= CPM_CFCR_UPE;
9.352 +#else
9.353 + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
9.354 + pll_div = pll_div ? 1 : 2 ;
9.355 + val = ( __cpm_get_pllout()/pll_div ) / pclk;
9.356 + val--;
9.357 + if ( val > 0x1ff ) {
9.358 + val = 0x1ff;
9.359 + }
9.360 + __cpm_set_pixdiv(val);
9.361 +
9.362 + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
9.363 + if ( val > 150000000 ) {
9.364 + val = 150000000;
9.365 + }
9.366 + val = ( __cpm_get_pllout()/pll_div ) / val;
9.367 + val--;
9.368 + if ( val > 0x1f ) {
9.369 + val = 0x1f;
9.370 + }
9.371 + __cpm_set_ldiv( val );
9.372 + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
9.373 +#endif
9.374 + __cpm_start_lcd();
9.375 + udelay(1000);
9.376 +
9.377 + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
9.378 +
9.379 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
9.380 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
9.381 + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
9.382 +
9.383 + return 0;
9.384 +}
9.385 +
9.386 +void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue)
9.387 +{
9.388 +}
9.389 +
9.390 +void lcd_initcolregs (void)
9.391 +{
9.392 +}
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
10.2 +++ b/stage2/jzlcd.h Tue Jun 09 21:10:40 2015 +0200
10.3 @@ -0,0 +1,103 @@
10.4 +/*
10.5 + * JzRISC lcd controller
10.6 + *
10.7 + * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
10.8 + *
10.9 + * This program is free software; you can redistribute it and/or
10.10 + * modify it under the terms of the GNU General Public License as
10.11 + * published by the Free Software Foundation; either version 2 of
10.12 + * the License, or (at your option) any later version.
10.13 + *
10.14 + * This program is distributed in the hope that it will be useful,
10.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10.17 + * GNU General Public License for more details.
10.18 + *
10.19 + * You should have received a copy of the GNU General Public License
10.20 + * along with this program; if not, write to the Free Software
10.21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
10.22 + * MA 02111-1307 USA
10.23 + */
10.24 +
10.25 +#ifndef __JZLCD_H__
10.26 +#define __JZLCD_H__
10.27 +
10.28 +unsigned long lcd_get_size(void);
10.29 +void lcd_ctrl_init(void *lcdbase);
10.30 +void lcd_enable(void);
10.31 +void lcd_disable(void);
10.32 +
10.33 +struct lcd_desc{
10.34 + unsigned int next_desc; /* LCDDAx */
10.35 + unsigned int databuf; /* LCDSAx */
10.36 + unsigned int frame_id; /* LCDFIDx */
10.37 + unsigned int cmd; /* LCDCMDx */
10.38 +};
10.39 +
10.40 +struct jzfb_info {
10.41 + unsigned int cfg; /* panel mode and pin usage etc. */
10.42 + unsigned int w;
10.43 + unsigned int h;
10.44 + unsigned int bpp; /* bit per pixel */
10.45 + unsigned int fclk; /* frame clk */
10.46 + unsigned int hsw; /* hsync width, in pclk */
10.47 + unsigned int vsw; /* vsync width, in line count */
10.48 + unsigned int elw; /* end of line, in pclk */
10.49 + unsigned int blw; /* begin of line, in pclk */
10.50 + unsigned int efw; /* end of frame, in line count */
10.51 + unsigned int bfw; /* begin of frame, in line count */
10.52 +};
10.53 +
10.54 +#define MODE_MASK 0x0f
10.55 +#define MODE_TFT_GEN 0x00
10.56 +#define MODE_TFT_SHARP 0x01
10.57 +#define MODE_TFT_CASIO 0x02
10.58 +#define MODE_TFT_SAMSUNG 0x03
10.59 +#define MODE_CCIR656_NONINT 0x04
10.60 +#define MODE_CCIR656_INT 0x05
10.61 +#define MODE_STN_COLOR_SINGLE 0x08
10.62 +#define MODE_STN_MONO_SINGLE 0x09
10.63 +#define MODE_STN_COLOR_DUAL 0x0a
10.64 +#define MODE_STN_MONO_DUAL 0x0b
10.65 +#define MODE_8BIT_SERIAL_TFT 0x0c
10.66 +
10.67 +#define MODE_TFT_18BIT (1<<7)
10.68 +
10.69 +#define STN_DAT_PIN1 (0x00 << 4)
10.70 +#define STN_DAT_PIN2 (0x01 << 4)
10.71 +#define STN_DAT_PIN4 (0x02 << 4)
10.72 +#define STN_DAT_PIN8 (0x03 << 4)
10.73 +#define STN_DAT_PINMASK STN_DAT_PIN8
10.74 +
10.75 +#define STFT_PSHI (1 << 15)
10.76 +#define STFT_CLSHI (1 << 14)
10.77 +#define STFT_SPLHI (1 << 13)
10.78 +#define STFT_REVHI (1 << 12)
10.79 +
10.80 +#define SYNC_MASTER (0 << 16)
10.81 +#define SYNC_SLAVE (1 << 16)
10.82 +
10.83 +#define DE_P (0 << 9)
10.84 +#define DE_N (1 << 9)
10.85 +
10.86 +#define PCLK_P (0 << 10)
10.87 +#define PCLK_N (1 << 10)
10.88 +
10.89 +#define HSYNC_P (0 << 11)
10.90 +#define HSYNC_N (1 << 11)
10.91 +
10.92 +#define VSYNC_P (0 << 8)
10.93 +#define VSYNC_N (1 << 8)
10.94 +
10.95 +#define DATA_NORMAL (0 << 17)
10.96 +#define DATA_INVERSE (1 << 17)
10.97 +
10.98 +
10.99 +/* Jz LCDFB supported I/O controls. */
10.100 +#define FBIOSETBACKLIGHT 0x4688
10.101 +#define FBIODISPON 0x4689
10.102 +#define FBIODISPOFF 0x468a
10.103 +#define FBIORESET 0x468b
10.104 +#define FBIOPRINT_REG 0x468c
10.105 +
10.106 +#endif /* __JZLCD_H__ */
11.1 --- a/stage2/lcd.c Tue Jun 09 00:03:27 2015 +0200
11.2 +++ b/stage2/lcd.c Tue Jun 09 21:10:40 2015 +0200
11.3 @@ -1,8 +1,8 @@
11.4 /*
11.5 * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools.
11.6 *
11.7 + * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
11.8 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
11.9 - * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
11.10 *
11.11 * This program is free software; you can redistribute it and/or modify it under
11.12 * the terms of the GNU General Public License as published by the Free Software
11.13 @@ -20,7 +20,9 @@
11.14
11.15 #include "xburst_types.h"
11.16 #include "nanonote_gpm940b0.h"
11.17 -#include "board-nanonote.h"
11.18 +#include "jzlcd.h"
11.19 +#include "sdram.h"
11.20 +#include "board.h"
11.21
11.22 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
11.23 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
12.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
12.2 +++ b/stage2/minipc_claa070vc01.c Tue Jun 09 21:10:40 2015 +0200
12.3 @@ -0,0 +1,33 @@
12.4 +/*
12.5 + * Minibook screen details
12.6 + *
12.7 + * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
12.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
12.9 + *
12.10 + * This program is free software; you can redistribute it and/or
12.11 + * modify it under the terms of the GNU General Public License as
12.12 + * published by the Free Software Foundation; either version 2 of
12.13 + * the License, or (at your option) any later version.
12.14 + *
12.15 + * This program is distributed in the hope that it will be useful,
12.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12.18 + * GNU General Public License for more details.
12.19 + *
12.20 + * You should have received a copy of the GNU General Public License
12.21 + * along with this program; if not, write to the Free Software
12.22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
12.23 + * MA 02111-1307 USA
12.24 + */
12.25 +
12.26 +#include "minipc_claa070vc01.h"
12.27 +#include "jzlcd.h"
12.28 +
12.29 +struct jzfb_info jzfb = {
12.30 + MODE_GENERIC_TFT | PCLK_N | HSYNC_N | VSYNC_N,
12.31 + 800, 480, 16, 60, 80, 20, 0, 0, 0, 0
12.32 +};
12.33 +
12.34 +vidinfo_t panel_info = {
12.35 + 800, 480, LCD_BPP,
12.36 +};
13.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
13.2 +++ b/stage2/minipc_claa070vc01.h Tue Jun 09 21:10:40 2015 +0200
13.3 @@ -0,0 +1,26 @@
13.4 +/*
13.5 + * Minibook panel-specific definitions
13.6 + *
13.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
13.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
13.9 + *
13.10 + * This program is free software; you can redistribute it and/or
13.11 + * modify it under the terms of the GNU General Public License as
13.12 + * published by the Free Software Foundation; either version 2 of
13.13 + * the License, or (at your option) any later version.
13.14 + *
13.15 + * This program is distributed in the hope that it will be useful,
13.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
13.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13.18 + * GNU General Public License for more details.
13.19 + *
13.20 + * You should have received a copy of the GNU General Public License
13.21 + * along with this program; if not, write to the Free Software
13.22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
13.23 + * MA 02111-1307 USA
13.24 + */
13.25 +
13.26 +#ifndef __MINIPC_CLAA070VC01_H__
13.27 +#define __MINIPC_CLAA070VC01_H__
13.28 +
13.29 +#endif /* __MINIPC_CLAA070VC01_H__ */
14.1 --- a/stage2/nanonote_gpm940b0.c Tue Jun 09 00:03:27 2015 +0200
14.2 +++ b/stage2/nanonote_gpm940b0.c Tue Jun 09 21:10:40 2015 +0200
14.3 @@ -1,5 +1,5 @@
14.4 /*
14.5 - * JzRISC lcd controller
14.6 + * Ben NanoNote screen details
14.7 *
14.8 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
14.9 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
14.10 @@ -20,33 +20,10 @@
14.11 * MA 02111-1307 USA
14.12 */
14.13
14.14 -/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h
14.15 - via u-boot/arch/mips/include/asm/io.h */
14.16 -/* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */
14.17 -#define virt_to_phys(n) ((int) n)
14.18 -
14.19 #include "nanonote_gpm940b0.h"
14.20 -#include "board-nanonote.h"
14.21 -
14.22 -#define align2(n) (n)=((((n)+1)>>1)<<1)
14.23 -#define align4(n) (n)=((((n)+3)>>2)<<2)
14.24 -#define align8(n) (n)=((((n)+7)>>3)<<3)
14.25 +#include "jzlcd.h"
14.26
14.27 -struct jzfb_info {
14.28 - unsigned int cfg; /* panel mode and pin usage etc. */
14.29 - unsigned int w;
14.30 - unsigned int h;
14.31 - unsigned int bpp; /* bit per pixel */
14.32 - unsigned int fclk; /* frame clk */
14.33 - unsigned int hsw; /* hsync width, in pclk */
14.34 - unsigned int vsw; /* vsync width, in line count */
14.35 - unsigned int elw; /* end of line, in pclk */
14.36 - unsigned int blw; /* begin of line, in pclk */
14.37 - unsigned int efw; /* end of frame, in line count */
14.38 - unsigned int bfw; /* begin of frame, in line count */
14.39 -};
14.40 -
14.41 -static struct jzfb_info jzfb = {
14.42 +struct jzfb_info jzfb = {
14.43 MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
14.44 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
14.45 };
14.46 @@ -54,350 +31,3 @@
14.47 vidinfo_t panel_info = {
14.48 320, 240, LCD_BPP,
14.49 };
14.50 -
14.51 -unsigned long lcd_get_size(void)
14.52 -{
14.53 - int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
14.54 - return line_length * panel_info.vl_row;
14.55 -}
14.56 -
14.57 -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
14.58 -static void jz_lcd_desc_init(vidinfo_t *vid);
14.59 -static int jz_lcd_hw_init(vidinfo_t *vid);
14.60 -
14.61 -void lcd_ctrl_init (void *lcdbase)
14.62 -{
14.63 - jz_lcd_init_mem(lcdbase, &panel_info);
14.64 - jz_lcd_desc_init(&panel_info);
14.65 - jz_lcd_hw_init(&panel_info);
14.66 -}
14.67 -
14.68 -/*
14.69 - * Before enabled lcd controller, lcd registers should be configured correctly.
14.70 - */
14.71 -void lcd_enable (void)
14.72 -{
14.73 - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
14.74 - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
14.75 -}
14.76 -
14.77 -void lcd_disable (void)
14.78 -{
14.79 - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
14.80 - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
14.81 -}
14.82 -
14.83 -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
14.84 -{
14.85 - unsigned long palette_mem_size;
14.86 - struct jz_fb_info *fbi = &vid->jz_fb;
14.87 - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
14.88 -
14.89 - fbi->screen = (unsigned long)lcdbase;
14.90 - fbi->palette_size = 256;
14.91 - palette_mem_size = fbi->palette_size * sizeof(u16);
14.92 -
14.93 - /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */
14.94 - /* locate palette and descs at end of page following fb */
14.95 - fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
14.96 -
14.97 - return 0;
14.98 -}
14.99 -
14.100 -static void jz_lcd_desc_init(vidinfo_t *vid)
14.101 -{
14.102 - struct jz_fb_info * fbi;
14.103 - fbi = &vid->jz_fb;
14.104 - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
14.105 - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
14.106 - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
14.107 -
14.108 - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
14.109 -
14.110 - /* populate descriptors */
14.111 - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
14.112 - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
14.113 - fbi->dmadesc_fblow->fidr = 0;
14.114 - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
14.115 -
14.116 - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
14.117 -
14.118 - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
14.119 - fbi->dmadesc_fbhigh->fidr = 0;
14.120 - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
14.121 -
14.122 - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
14.123 - fbi->dmadesc_palette->fidr = 0;
14.124 - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
14.125 -
14.126 - if(NBITS(vid->vl_bpix) < 12)
14.127 - {
14.128 - /* assume any mode with <12 bpp is palette driven */
14.129 - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
14.130 - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
14.131 - /* flips back and forth between pal and fbhigh */
14.132 - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
14.133 - } else {
14.134 - /* palette shouldn't be loaded in true-color mode */
14.135 - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
14.136 - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
14.137 - }
14.138 -
14.139 - flush_cache_all();
14.140 -}
14.141 -
14.142 -static int jz_lcd_hw_init(vidinfo_t *vid)
14.143 -{
14.144 - struct jz_fb_info *fbi = &vid->jz_fb;
14.145 - unsigned int val = 0;
14.146 - unsigned int pclk;
14.147 - unsigned int stnH;
14.148 - int pll_div;
14.149 -
14.150 - /* Setting Control register */
14.151 - switch (jzfb.bpp) {
14.152 - case 1:
14.153 - val |= LCD_CTRL_BPP_1;
14.154 - break;
14.155 - case 2:
14.156 - val |= LCD_CTRL_BPP_2;
14.157 - break;
14.158 - case 4:
14.159 - val |= LCD_CTRL_BPP_4;
14.160 - break;
14.161 - case 8:
14.162 - val |= LCD_CTRL_BPP_8;
14.163 - break;
14.164 - case 15:
14.165 - val |= LCD_CTRL_RGB555;
14.166 - case 16:
14.167 - val |= LCD_CTRL_BPP_16;
14.168 - break;
14.169 - case 17 ... 32:
14.170 - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
14.171 - break;
14.172 -
14.173 - default:
14.174 - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */
14.175 - val |= LCD_CTRL_BPP_16;
14.176 - break;
14.177 - }
14.178 -
14.179 - switch (jzfb.cfg & MODE_MASK) {
14.180 - case MODE_STN_MONO_DUAL:
14.181 - case MODE_STN_COLOR_DUAL:
14.182 - case MODE_STN_MONO_SINGLE:
14.183 - case MODE_STN_COLOR_SINGLE:
14.184 - switch (jzfb.bpp) {
14.185 - case 1:
14.186 - /* val |= LCD_CTRL_PEDN; */
14.187 - case 2:
14.188 - val |= LCD_CTRL_FRC_2;
14.189 - break;
14.190 - case 4:
14.191 - val |= LCD_CTRL_FRC_4;
14.192 - break;
14.193 - case 8:
14.194 - default:
14.195 - val |= LCD_CTRL_FRC_16;
14.196 - break;
14.197 - }
14.198 - break;
14.199 - }
14.200 -
14.201 - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
14.202 - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
14.203 -
14.204 - switch (jzfb.cfg & MODE_MASK) {
14.205 - case MODE_STN_MONO_DUAL:
14.206 - case MODE_STN_COLOR_DUAL:
14.207 - case MODE_STN_MONO_SINGLE:
14.208 - case MODE_STN_COLOR_SINGLE:
14.209 - switch (jzfb.cfg & STN_DAT_PINMASK) {
14.210 - case STN_DAT_PIN1:
14.211 - /* Do not adjust the hori-param value. */
14.212 - break;
14.213 - case STN_DAT_PIN2:
14.214 - align2(jzfb.hsw);
14.215 - align2(jzfb.elw);
14.216 - align2(jzfb.blw);
14.217 - break;
14.218 - case STN_DAT_PIN4:
14.219 - align4(jzfb.hsw);
14.220 - align4(jzfb.elw);
14.221 - align4(jzfb.blw);
14.222 - break;
14.223 - case STN_DAT_PIN8:
14.224 - align8(jzfb.hsw);
14.225 - align8(jzfb.elw);
14.226 - align8(jzfb.blw);
14.227 - break;
14.228 - }
14.229 - break;
14.230 - }
14.231 -
14.232 - REG_LCD_CTRL = val;
14.233 -
14.234 - switch (jzfb.cfg & MODE_MASK) {
14.235 - case MODE_STN_MONO_DUAL:
14.236 - case MODE_STN_COLOR_DUAL:
14.237 - case MODE_STN_MONO_SINGLE:
14.238 - case MODE_STN_COLOR_SINGLE:
14.239 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
14.240 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
14.241 - stnH = jzfb.h >> 1;
14.242 - else
14.243 - stnH = jzfb.h;
14.244 -
14.245 - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
14.246 - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
14.247 -
14.248 - /* Screen setting */
14.249 - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
14.250 - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
14.251 - REG_LCD_DAV = (0 << 16) | (stnH);
14.252 -
14.253 - /* AC BIAs signal */
14.254 - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
14.255 -
14.256 - break;
14.257 -
14.258 - case MODE_TFT_GEN:
14.259 - case MODE_TFT_SHARP:
14.260 - case MODE_TFT_CASIO:
14.261 - case MODE_TFT_SAMSUNG:
14.262 - case MODE_8BIT_SERIAL_TFT:
14.263 - case MODE_TFT_18BIT:
14.264 - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
14.265 - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
14.266 - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
14.267 - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
14.268 - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
14.269 - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
14.270 - break;
14.271 - }
14.272 -
14.273 - switch (jzfb.cfg & MODE_MASK) {
14.274 - case MODE_TFT_SAMSUNG:
14.275 - {
14.276 - unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
14.277 - unsigned int rev_s, rev_e, inv_s, inv_e;
14.278 -
14.279 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
14.280 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
14.281 -
14.282 - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
14.283 - tp_s = jzfb.blw + jzfb.w + 1;
14.284 - tp_e = tp_s + 1;
14.285 - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
14.286 - ckv_s = tp_s - pclk/(1000000000/4100);
14.287 - ckv_e = tp_s + total;
14.288 - rev_s = tp_s - 11; /* -11.5 clk */
14.289 - rev_e = rev_s + total;
14.290 - inv_s = tp_s;
14.291 - inv_e = inv_s + total;
14.292 - REG_LCD_CLS = (tp_s << 16) | tp_e;
14.293 - REG_LCD_PS = (ckv_s << 16) | ckv_e;
14.294 - REG_LCD_SPL = (rev_s << 16) | rev_e;
14.295 - REG_LCD_REV = (inv_s << 16) | inv_e;
14.296 - jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
14.297 - break;
14.298 - }
14.299 - case MODE_TFT_SHARP:
14.300 - {
14.301 - unsigned int total, cls_s, cls_e, ps_s, ps_e;
14.302 - unsigned int spl_s, spl_e, rev_s, rev_e;
14.303 - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
14.304 - spl_s = 1;
14.305 - spl_e = spl_s + 1;
14.306 - cls_s = 0;
14.307 - cls_e = total - 60; /* > 4us (pclk = 80ns) */
14.308 - ps_s = cls_s;
14.309 - ps_e = cls_e;
14.310 - rev_s = total - 40; /* > 3us (pclk = 80ns) */
14.311 - rev_e = rev_s + total;
14.312 - jzfb.cfg |= STFT_PSHI;
14.313 - REG_LCD_SPL = (spl_s << 16) | spl_e;
14.314 - REG_LCD_CLS = (cls_s << 16) | cls_e;
14.315 - REG_LCD_PS = (ps_s << 16) | ps_e;
14.316 - REG_LCD_REV = (rev_s << 16) | rev_e;
14.317 - break;
14.318 - }
14.319 - case MODE_TFT_CASIO:
14.320 - break;
14.321 - }
14.322 -
14.323 - /* Configure the LCD panel */
14.324 - REG_LCD_CFG = jzfb.cfg;
14.325 -
14.326 - /* Timing setting */
14.327 - __cpm_stop_lcd();
14.328 -
14.329 - val = jzfb.fclk; /* frame clk */
14.330 - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
14.331 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
14.332 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
14.333 - } else {
14.334 - /* serial mode: Hsync period = 3*Width_Pixel */
14.335 - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
14.336 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
14.337 - }
14.338 -
14.339 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
14.340 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
14.341 - pclk = (pclk * 3);
14.342 -
14.343 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
14.344 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
14.345 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
14.346 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
14.347 - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
14.348 -
14.349 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
14.350 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
14.351 - pclk >>= 1;
14.352 -
14.353 - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
14.354 - pll_div = pll_div ? 1 : 2 ;
14.355 - val = ( __cpm_get_pllout()/pll_div ) / pclk;
14.356 - val--;
14.357 - if ( val > 0x1ff ) {
14.358 - /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */
14.359 - val = 0x1ff;
14.360 - }
14.361 - __cpm_set_pixdiv(val);
14.362 -
14.363 - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
14.364 - if ( val > 150000000 ) {
14.365 - /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */
14.366 - /* printf("Change LCDClock to 150MHz\n"); */
14.367 - val = 150000000;
14.368 - }
14.369 - val = ( __cpm_get_pllout()/pll_div ) / val;
14.370 - val--;
14.371 - if ( val > 0x1f ) {
14.372 - /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */
14.373 - val = 0x1f;
14.374 - }
14.375 - __cpm_set_ldiv( val );
14.376 - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
14.377 -
14.378 - __cpm_start_lcd();
14.379 - udelay(1000);
14.380 -
14.381 - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
14.382 -
14.383 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
14.384 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
14.385 - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
14.386 -
14.387 - return 0;
14.388 -}
14.389 -
14.390 -void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue)
14.391 -{
14.392 -}
14.393 -
14.394 -void lcd_initcolregs (void)
14.395 -{
14.396 -}
15.1 --- a/stage2/nanonote_gpm940b0.h Tue Jun 09 00:03:27 2015 +0200
15.2 +++ b/stage2/nanonote_gpm940b0.h Tue Jun 09 21:10:40 2015 +0200
15.3 @@ -1,7 +1,8 @@
15.4 /*
15.5 - * JzRISC lcd controller
15.6 + * Ben NanoNote panel-specific definitions
15.7 *
15.8 - * Xiangfu Liu <xiangfu@sharism.cc>
15.9 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
15.10 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
15.11 *
15.12 * This program is free software; you can redistribute it and/or
15.13 * modify it under the terms of the GNU General Public License as
15.14 @@ -25,75 +26,6 @@
15.15 #include "nanonote.h"
15.16 #include "jz4740.h"
15.17
15.18 -unsigned long lcd_get_size(void);
15.19 -void lcd_ctrl_init(void *lcdbase);
15.20 -void lcd_enable(void);
15.21 -void lcd_disable(void);
15.22 -
15.23 -struct lcd_desc{
15.24 - unsigned int next_desc; /* LCDDAx */
15.25 - unsigned int databuf; /* LCDSAx */
15.26 - unsigned int frame_id; /* LCDFIDx */
15.27 - unsigned int cmd; /* LCDCMDx */
15.28 -};
15.29 -
15.30 -#define MODE_MASK 0x0f
15.31 -#define MODE_TFT_GEN 0x00
15.32 -#define MODE_TFT_SHARP 0x01
15.33 -#define MODE_TFT_CASIO 0x02
15.34 -#define MODE_TFT_SAMSUNG 0x03
15.35 -#define MODE_CCIR656_NONINT 0x04
15.36 -#define MODE_CCIR656_INT 0x05
15.37 -#define MODE_STN_COLOR_SINGLE 0x08
15.38 -#define MODE_STN_MONO_SINGLE 0x09
15.39 -#define MODE_STN_COLOR_DUAL 0x0a
15.40 -#define MODE_STN_MONO_DUAL 0x0b
15.41 -#define MODE_8BIT_SERIAL_TFT 0x0c
15.42 -
15.43 -#define MODE_TFT_18BIT (1<<7)
15.44 -
15.45 -#define STN_DAT_PIN1 (0x00 << 4)
15.46 -#define STN_DAT_PIN2 (0x01 << 4)
15.47 -#define STN_DAT_PIN4 (0x02 << 4)
15.48 -#define STN_DAT_PIN8 (0x03 << 4)
15.49 -#define STN_DAT_PINMASK STN_DAT_PIN8
15.50 -
15.51 -#define STFT_PSHI (1 << 15)
15.52 -#define STFT_CLSHI (1 << 14)
15.53 -#define STFT_SPLHI (1 << 13)
15.54 -#define STFT_REVHI (1 << 12)
15.55 -
15.56 -#define SYNC_MASTER (0 << 16)
15.57 -#define SYNC_SLAVE (1 << 16)
15.58 -
15.59 -#define DE_P (0 << 9)
15.60 -#define DE_N (1 << 9)
15.61 -
15.62 -#define PCLK_P (0 << 10)
15.63 -#define PCLK_N (1 << 10)
15.64 -
15.65 -#define HSYNC_P (0 << 11)
15.66 -#define HSYNC_N (1 << 11)
15.67 -
15.68 -#define VSYNC_P (0 << 8)
15.69 -#define VSYNC_N (1 << 8)
15.70 -
15.71 -#define DATA_NORMAL (0 << 17)
15.72 -#define DATA_INVERSE (1 << 17)
15.73 -
15.74 -
15.75 -/* Jz LCDFB supported I/O controls. */
15.76 -#define FBIOSETBACKLIGHT 0x4688
15.77 -#define FBIODISPON 0x4689
15.78 -#define FBIODISPOFF 0x468a
15.79 -#define FBIORESET 0x468b
15.80 -#define FBIOPRINT_REG 0x468c
15.81 -
15.82 -/*
15.83 - * LCD panel specific definition
15.84 - */
15.85 -#define MODE (0xc9) /* 8bit serial RGB */
15.86 -
15.87 #define __spi_write_reg1(reg, val) \
15.88 do { \
15.89 unsigned char no; \
16.1 --- a/stage2/stage2.c Tue Jun 09 00:03:27 2015 +0200
16.2 +++ b/stage2/stage2.c Tue Jun 09 21:10:40 2015 +0200
16.3 @@ -1,8 +1,8 @@
16.4 /*
16.5 * Ben NanoNote stage 2 payload test.
16.6 *
16.7 + * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
16.8 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
16.9 - * Copyright (C) Wolfgang Spraul <wolfgang@sharism.cc>
16.10 *
16.11 * This program is free software; you can redistribute it and/or modify it under
16.12 * the terms of the GNU General Public License as published by the Free Software