1.1 --- a/Makefile Sun Jun 07 02:20:54 2015 +0200
1.2 +++ b/Makefile Sun Jun 07 18:21:24 2015 +0200
1.3 @@ -28,7 +28,7 @@
1.4 # NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888
1.5
1.6 ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include
1.7 -CFLAGS = -O2 -Wall -fno-pic -fno-unit-at-a-time -fno-zero-initialized-in-bss \
1.8 +CFLAGS = -O2 -Wall -fno-unit-at-a-time -fno-zero-initialized-in-bss \
1.9 -ffreestanding -fno-hosted -fno-builtin \
1.10 -march=mips32 -mno-abicalls \
1.11 -Iinclude -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic
1.12 @@ -42,9 +42,9 @@
1.13 # Ordering of objects is important and cannot be left to replacement rules.
1.14
1.15 SRC1 = head1.S stage1.c board-nanonote.c
1.16 -SRC2 = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c
1.17 +SRC2 = head2.S stage2.c board-nanonote2.c nanonote_gpm940b0.c lcd.c
1.18 OBJ1 = head1.o stage1.o board-nanonote.o
1.19 -OBJ2 = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o
1.20 +OBJ2 = head2.o stage2.o board-nanonote2.o nanonote_gpm940b0.o lcd.o
1.21 OBJ = $(OBJ1) $(OBJ2)
1.22
1.23 .PHONY: all clean distclean
1.24 @@ -61,7 +61,7 @@
1.25 $(OBJCOPY) -O binary $(@:.bin=.elf) $@+
1.26 $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump)
1.27 $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map)
1.28 - $(NM) -n $< > System-$(@:.bin=.map)
1.29 + $(NM) -n $(@:.bin=.elf) > System-$(@:.bin=.map)
1.30 chmod -x $@+
1.31 mv -f $@+ $@
1.32
2.1 --- a/board-nanonote.c Sun Jun 07 02:20:54 2015 +0200
2.2 +++ b/board-nanonote.c Sun Jun 07 18:21:24 2015 +0200
2.3 @@ -80,72 +80,6 @@
2.4 __gpio_as_sdram_32bit();
2.5 }
2.6
2.7 -void gpio_init2(void)
2.8 -{
2.9 - /*
2.10 - * Initialize LCD pins
2.11 - */
2.12 - __gpio_as_slcd_8bit();
2.13 -
2.14 - /*
2.15 - * Initialize MSC pins
2.16 - */
2.17 - __gpio_as_msc();
2.18 -
2.19 - /*
2.20 - * Initialize Other pins
2.21 - */
2.22 - unsigned int i;
2.23 - for (i = 0; i < 7; i++){
2.24 - __gpio_as_input(GPIO_KEYIN_BASE + i);
2.25 - __gpio_enable_pull(GPIO_KEYIN_BASE + i);
2.26 - }
2.27 -
2.28 - for (i = 0; i < 8; i++) {
2.29 - __gpio_as_output(GPIO_KEYOUT_BASE + i);
2.30 - __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
2.31 - }
2.32 -
2.33 - /* enable the TP4, TP5 as UART0 */
2.34 - __gpio_jtag_to_uart0();
2.35 -
2.36 - __gpio_as_input(GPIO_KEYIN_8);
2.37 - __gpio_enable_pull(GPIO_KEYIN_8);
2.38 -
2.39 - __gpio_as_output(GPIO_AUDIO_POP);
2.40 - __gpio_set_pin(GPIO_AUDIO_POP);
2.41 -
2.42 - __gpio_as_output(GPIO_LCD_CS);
2.43 - __gpio_clear_pin(GPIO_LCD_CS);
2.44 -
2.45 - __gpio_as_output(GPIO_AMP_EN);
2.46 - __gpio_clear_pin(GPIO_AMP_EN);
2.47 -
2.48 - __gpio_as_output(GPIO_SDPW_EN);
2.49 - __gpio_disable_pull(GPIO_SDPW_EN);
2.50 - __gpio_clear_pin(GPIO_SDPW_EN);
2.51 -
2.52 - __gpio_as_input(GPIO_SD_DETECT);
2.53 - __gpio_disable_pull(GPIO_SD_DETECT);
2.54 -
2.55 - __gpio_as_input(GPIO_USB_DETECT);
2.56 - __gpio_enable_pull(GPIO_USB_DETECT);
2.57 -}
2.58 -
2.59 -void cpm_init(void)
2.60 -{
2.61 - __cpm_stop_ipu();
2.62 - __cpm_stop_cim();
2.63 - __cpm_stop_i2c();
2.64 - __cpm_stop_ssi();
2.65 - __cpm_stop_uart1();
2.66 - __cpm_stop_sadc();
2.67 - __cpm_stop_uhc();
2.68 - __cpm_stop_udc();
2.69 - __cpm_stop_aic1();
2.70 -/* __cpm_stop_aic2();*/
2.71 -}
2.72 -
2.73 void pll_init(void)
2.74 {
2.75 register unsigned int cfcr, plcr1;
2.76 @@ -278,244 +212,3 @@
2.77
2.78 /* everything is ok now */
2.79 }
2.80 -
2.81 -void rtc_init(void)
2.82 -{
2.83 - while ( !__rtc_write_ready());
2.84 - __rtc_enable_alarm(); /* enable alarm */
2.85 -
2.86 - while ( !__rtc_write_ready());
2.87 - REG_RTC_RGR = 0x00007fff; /* type value */
2.88 -
2.89 - while ( !__rtc_write_ready());
2.90 - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
2.91 -
2.92 - while ( !__rtc_write_ready());
2.93 - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
2.94 -}
2.95 -
2.96 -unsigned long get_memory_size(void)
2.97 -{
2.98 - unsigned int dmcr;
2.99 - unsigned int rows, cols, dw, banks;
2.100 - unsigned long size;
2.101 -
2.102 - dmcr = REG_EMC_DMCR;
2.103 - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
2.104 - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
2.105 - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
2.106 - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
2.107 -
2.108 - size = (1 << (rows + cols)) * dw * banks;
2.109 -
2.110 - return size;
2.111 -}
2.112 -
2.113 -/* Timer routines. */
2.114 -
2.115 -#define TIMER_CHAN 0
2.116 -#define TIMER_FDATA 0xffff /* Timer full data value */
2.117 -#define TIMER_HZ CONFIG_SYS_HZ
2.118 -
2.119 -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
2.120 -
2.121 -static unsigned long timestamp;
2.122 -static unsigned long lastdec;
2.123 -
2.124 -void reset_timer_masked(void);
2.125 -unsigned long get_timer_masked(void);
2.126 -void udelay_masked(unsigned long usec);
2.127 -
2.128 -/*
2.129 - * timer without interrupts
2.130 - */
2.131 -
2.132 -int timer_init(void)
2.133 -{
2.134 - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
2.135 - REG_TCU_TCNT(TIMER_CHAN) = 0;
2.136 - REG_TCU_TDHR(TIMER_CHAN) = 0;
2.137 - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
2.138 -
2.139 - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
2.140 - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
2.141 - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
2.142 -
2.143 - lastdec = 0;
2.144 - timestamp = 0;
2.145 -
2.146 - return 0;
2.147 -}
2.148 -
2.149 -void reset_timer(void)
2.150 -{
2.151 - reset_timer_masked ();
2.152 -}
2.153 -
2.154 -unsigned long get_timer(unsigned long base)
2.155 -{
2.156 - return get_timer_masked () - base;
2.157 -}
2.158 -
2.159 -void set_timer(unsigned long t)
2.160 -{
2.161 - timestamp = t;
2.162 -}
2.163 -
2.164 -void udelay (unsigned long usec)
2.165 -{
2.166 - unsigned long tmo,tmp;
2.167 -
2.168 - /* normalize */
2.169 - if (usec >= 1000) {
2.170 - tmo = usec / 1000;
2.171 - tmo *= TIMER_HZ;
2.172 - tmo /= 1000;
2.173 - }
2.174 - else {
2.175 - if (usec >= 1) {
2.176 - tmo = usec * TIMER_HZ;
2.177 - tmo /= (1000*1000);
2.178 - }
2.179 - else
2.180 - tmo = 1;
2.181 - }
2.182 -
2.183 - /* check for rollover during this delay */
2.184 - tmp = get_timer (0);
2.185 - if ((tmp + tmo) < tmp )
2.186 - reset_timer_masked(); /* timer would roll over */
2.187 - else
2.188 - tmo += tmp;
2.189 -
2.190 - while (get_timer_masked () < tmo);
2.191 -}
2.192 -
2.193 -void reset_timer_masked (void)
2.194 -{
2.195 - /* reset time */
2.196 - lastdec = READ_TIMER;
2.197 - timestamp = 0;
2.198 -}
2.199 -
2.200 -unsigned long get_timer_masked (void)
2.201 -{
2.202 - unsigned long now = READ_TIMER;
2.203 -
2.204 - if (lastdec <= now) {
2.205 - /* normal mode */
2.206 - timestamp += (now - lastdec);
2.207 - } else {
2.208 - /* we have an overflow ... */
2.209 - timestamp += TIMER_FDATA + now - lastdec;
2.210 - }
2.211 - lastdec = now;
2.212 -
2.213 - return timestamp;
2.214 -}
2.215 -
2.216 -void udelay_masked (unsigned long usec)
2.217 -{
2.218 - unsigned long tmo;
2.219 - unsigned long endtime;
2.220 - signed long diff;
2.221 -
2.222 - /* normalize */
2.223 - if (usec >= 1000) {
2.224 - tmo = usec / 1000;
2.225 - tmo *= TIMER_HZ;
2.226 - tmo /= 1000;
2.227 - } else {
2.228 - if (usec > 1) {
2.229 - tmo = usec * TIMER_HZ;
2.230 - tmo /= (1000*1000);
2.231 - } else {
2.232 - tmo = 1;
2.233 - }
2.234 - }
2.235 -
2.236 - endtime = get_timer_masked () + tmo;
2.237 -
2.238 - do {
2.239 - unsigned long now = get_timer_masked ();
2.240 - diff = endtime - now;
2.241 - } while (diff >= 0);
2.242 -}
2.243 -
2.244 -/*
2.245 - * This function is derived from PowerPC code (read timebase as long long).
2.246 - * On MIPS it just returns the timer value.
2.247 - */
2.248 -unsigned long long get_ticks(void)
2.249 -{
2.250 - return get_timer(0);
2.251 -}
2.252 -
2.253 -/*
2.254 - * This function is derived from PowerPC code (timebase clock frequency).
2.255 - * On MIPS it returns the number of timer ticks per second.
2.256 - */
2.257 -unsigned long get_tbclk (void)
2.258 -{
2.259 - return TIMER_HZ;
2.260 -}
2.261 -
2.262 -/* CPU-specific routines from U-Boot.
2.263 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
2.264 - See: u-boot/arch/mips/include/asm/cacheops.h
2.265 -*/
2.266 -
2.267 -#define Index_Store_Tag_I 0x08
2.268 -#define Index_Writeback_Inv_D 0x15
2.269 -
2.270 -void flush_icache_all(void)
2.271 -{
2.272 - u32 addr, t = 0;
2.273 -
2.274 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
2.275 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
2.276 -
2.277 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
2.278 - addr += CONFIG_SYS_CACHELINE_SIZE) {
2.279 - asm volatile (
2.280 - ".set mips3\n\t"
2.281 - " cache %0, 0(%1)\n\t"
2.282 - ".set mips2\n\t"
2.283 - :
2.284 - : "I" (Index_Store_Tag_I), "r"(addr));
2.285 - }
2.286 -
2.287 - /* invalicate btb */
2.288 - asm volatile (
2.289 - ".set mips32\n\t"
2.290 - "mfc0 %0, $16, 7\n\t"
2.291 - "nop\n\t"
2.292 - "ori %0,2\n\t"
2.293 - "mtc0 %0, $16, 7\n\t"
2.294 - ".set mips2\n\t"
2.295 - :
2.296 - : "r" (t));
2.297 -}
2.298 -
2.299 -void flush_dcache_all(void)
2.300 -{
2.301 - u32 addr;
2.302 -
2.303 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
2.304 - addr += CONFIG_SYS_CACHELINE_SIZE) {
2.305 - asm volatile (
2.306 - ".set mips3\n\t"
2.307 - " cache %0, 0(%1)\n\t"
2.308 - ".set mips2\n\t"
2.309 - :
2.310 - : "I" (Index_Writeback_Inv_D), "r"(addr));
2.311 - }
2.312 -
2.313 - asm volatile ("sync");
2.314 -}
2.315 -
2.316 -void flush_cache_all(void)
2.317 -{
2.318 - flush_dcache_all();
2.319 - flush_icache_all();
2.320 -}
3.1 --- a/board-nanonote.h Sun Jun 07 02:20:54 2015 +0200
3.2 +++ b/board-nanonote.h Sun Jun 07 18:21:24 2015 +0200
3.3 @@ -5,17 +5,7 @@
3.4
3.5 void load_args(void);
3.6 void gpio_init(void);
3.7 -void gpio_init2(void);
3.8 -void cpm_init(void);
3.9 void pll_init(void);
3.10 void sdram_init(void);
3.11 -void rtc_init(void);
3.12 -int timer_init(void);
3.13 -
3.14 -/* Utility functions. */
3.15 -
3.16 -void udelay(unsigned long usec);
3.17 -void flush_cache_all(void);
3.18 -unsigned long get_memory_size(void);
3.19
3.20 #endif /* __BOARD_NANONOTE_H__ */
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/board-nanonote2.c Sun Jun 07 18:21:24 2015 +0200
4.3 @@ -0,0 +1,334 @@
4.4 +/*
4.5 + * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools.
4.6 + *
4.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
4.8 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
4.9 + * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
4.10 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4.11 + *
4.12 + * This program is free software; you can redistribute it and/or modify it under
4.13 + * the terms of the GNU General Public License as published by the Free Software
4.14 + * Foundation; either version 3 of the License, or (at your option) any later
4.15 + * version.
4.16 + *
4.17 + * This program is distributed in the hope that it will be useful, but WITHOUT
4.18 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
4.19 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
4.20 + * details.
4.21 + *
4.22 + * You should have received a copy of the GNU General Public License along with
4.23 + * this program. If not, see <http://www.gnu.org/licenses/>.
4.24 + */
4.25 +
4.26 +#include "jz4740.h"
4.27 +#include "configs.h"
4.28 +#include "nanonote.h"
4.29 +
4.30 +/* Later initialisation functions. */
4.31 +
4.32 +void gpio_init2(void)
4.33 +{
4.34 + /*
4.35 + * Initialize LCD pins
4.36 + */
4.37 + __gpio_as_slcd_8bit();
4.38 +
4.39 + /*
4.40 + * Initialize MSC pins
4.41 + */
4.42 + __gpio_as_msc();
4.43 +
4.44 + /*
4.45 + * Initialize Other pins
4.46 + */
4.47 + unsigned int i;
4.48 + for (i = 0; i < 7; i++){
4.49 + __gpio_as_input(GPIO_KEYIN_BASE + i);
4.50 + __gpio_enable_pull(GPIO_KEYIN_BASE + i);
4.51 + }
4.52 +
4.53 + for (i = 0; i < 8; i++) {
4.54 + __gpio_as_output(GPIO_KEYOUT_BASE + i);
4.55 + __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
4.56 + }
4.57 +
4.58 + /* enable the TP4, TP5 as UART0 */
4.59 + __gpio_jtag_to_uart0();
4.60 +
4.61 + __gpio_as_input(GPIO_KEYIN_8);
4.62 + __gpio_enable_pull(GPIO_KEYIN_8);
4.63 +
4.64 + __gpio_as_output(GPIO_AUDIO_POP);
4.65 + __gpio_set_pin(GPIO_AUDIO_POP);
4.66 +
4.67 + __gpio_as_output(GPIO_LCD_CS);
4.68 + __gpio_clear_pin(GPIO_LCD_CS);
4.69 +
4.70 + __gpio_as_output(GPIO_AMP_EN);
4.71 + __gpio_clear_pin(GPIO_AMP_EN);
4.72 +
4.73 + __gpio_as_output(GPIO_SDPW_EN);
4.74 + __gpio_disable_pull(GPIO_SDPW_EN);
4.75 + __gpio_clear_pin(GPIO_SDPW_EN);
4.76 +
4.77 + __gpio_as_input(GPIO_SD_DETECT);
4.78 + __gpio_disable_pull(GPIO_SD_DETECT);
4.79 +
4.80 + __gpio_as_input(GPIO_USB_DETECT);
4.81 + __gpio_enable_pull(GPIO_USB_DETECT);
4.82 +}
4.83 +
4.84 +void cpm_init(void)
4.85 +{
4.86 + __cpm_stop_ipu();
4.87 + __cpm_stop_cim();
4.88 + __cpm_stop_i2c();
4.89 + __cpm_stop_ssi();
4.90 + __cpm_stop_uart1();
4.91 + __cpm_stop_sadc();
4.92 + __cpm_stop_uhc();
4.93 + __cpm_stop_udc();
4.94 + __cpm_stop_aic1();
4.95 +/* __cpm_stop_aic2();*/
4.96 +}
4.97 +
4.98 +void rtc_init(void)
4.99 +{
4.100 + while ( !__rtc_write_ready());
4.101 + __rtc_enable_alarm(); /* enable alarm */
4.102 +
4.103 + while ( !__rtc_write_ready());
4.104 + REG_RTC_RGR = 0x00007fff; /* type value */
4.105 +
4.106 + while ( !__rtc_write_ready());
4.107 + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
4.108 +
4.109 + while ( !__rtc_write_ready());
4.110 + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
4.111 +}
4.112 +
4.113 +unsigned long get_memory_size(void)
4.114 +{
4.115 + unsigned int dmcr;
4.116 + unsigned int rows, cols, dw, banks;
4.117 + unsigned long size;
4.118 +
4.119 + dmcr = REG_EMC_DMCR;
4.120 + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
4.121 + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
4.122 + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
4.123 + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
4.124 +
4.125 + size = (1 << (rows + cols)) * dw * banks;
4.126 +
4.127 + return size;
4.128 +}
4.129 +
4.130 +/* Timer routines. */
4.131 +
4.132 +#define TIMER_CHAN 0
4.133 +#define TIMER_FDATA 0xffff /* Timer full data value */
4.134 +#define TIMER_HZ CONFIG_SYS_HZ
4.135 +
4.136 +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
4.137 +
4.138 +static unsigned long timestamp;
4.139 +static unsigned long lastdec;
4.140 +
4.141 +void reset_timer_masked(void);
4.142 +unsigned long get_timer_masked(void);
4.143 +void udelay_masked(unsigned long usec);
4.144 +
4.145 +/*
4.146 + * timer without interrupts
4.147 + */
4.148 +
4.149 +int timer_init(void)
4.150 +{
4.151 + REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
4.152 + REG_TCU_TCNT(TIMER_CHAN) = 0;
4.153 + REG_TCU_TDHR(TIMER_CHAN) = 0;
4.154 + REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
4.155 +
4.156 + REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
4.157 + REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
4.158 + REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
4.159 +
4.160 + lastdec = 0;
4.161 + timestamp = 0;
4.162 +
4.163 + return 0;
4.164 +}
4.165 +
4.166 +void reset_timer(void)
4.167 +{
4.168 + reset_timer_masked ();
4.169 +}
4.170 +
4.171 +unsigned long get_timer(unsigned long base)
4.172 +{
4.173 + return get_timer_masked () - base;
4.174 +}
4.175 +
4.176 +void set_timer(unsigned long t)
4.177 +{
4.178 + timestamp = t;
4.179 +}
4.180 +
4.181 +void udelay (unsigned long usec)
4.182 +{
4.183 + unsigned long tmo,tmp;
4.184 +
4.185 + /* normalize */
4.186 + if (usec >= 1000) {
4.187 + tmo = usec / 1000;
4.188 + tmo *= TIMER_HZ;
4.189 + tmo /= 1000;
4.190 + }
4.191 + else {
4.192 + if (usec >= 1) {
4.193 + tmo = usec * TIMER_HZ;
4.194 + tmo /= (1000*1000);
4.195 + }
4.196 + else
4.197 + tmo = 1;
4.198 + }
4.199 +
4.200 + /* check for rollover during this delay */
4.201 + tmp = get_timer (0);
4.202 + if ((tmp + tmo) < tmp )
4.203 + reset_timer_masked(); /* timer would roll over */
4.204 + else
4.205 + tmo += tmp;
4.206 +
4.207 + while (get_timer_masked () < tmo);
4.208 +}
4.209 +
4.210 +void reset_timer_masked (void)
4.211 +{
4.212 + /* reset time */
4.213 + lastdec = READ_TIMER;
4.214 + timestamp = 0;
4.215 +}
4.216 +
4.217 +unsigned long get_timer_masked (void)
4.218 +{
4.219 + unsigned long now = READ_TIMER;
4.220 +
4.221 + if (lastdec <= now) {
4.222 + /* normal mode */
4.223 + timestamp += (now - lastdec);
4.224 + } else {
4.225 + /* we have an overflow ... */
4.226 + timestamp += TIMER_FDATA + now - lastdec;
4.227 + }
4.228 + lastdec = now;
4.229 +
4.230 + return timestamp;
4.231 +}
4.232 +
4.233 +void udelay_masked (unsigned long usec)
4.234 +{
4.235 + unsigned long tmo;
4.236 + unsigned long endtime;
4.237 + signed long diff;
4.238 +
4.239 + /* normalize */
4.240 + if (usec >= 1000) {
4.241 + tmo = usec / 1000;
4.242 + tmo *= TIMER_HZ;
4.243 + tmo /= 1000;
4.244 + } else {
4.245 + if (usec > 1) {
4.246 + tmo = usec * TIMER_HZ;
4.247 + tmo /= (1000*1000);
4.248 + } else {
4.249 + tmo = 1;
4.250 + }
4.251 + }
4.252 +
4.253 + endtime = get_timer_masked () + tmo;
4.254 +
4.255 + do {
4.256 + unsigned long now = get_timer_masked ();
4.257 + diff = endtime - now;
4.258 + } while (diff >= 0);
4.259 +}
4.260 +
4.261 +/*
4.262 + * This function is derived from PowerPC code (read timebase as long long).
4.263 + * On MIPS it just returns the timer value.
4.264 + */
4.265 +unsigned long long get_ticks(void)
4.266 +{
4.267 + return get_timer(0);
4.268 +}
4.269 +
4.270 +/*
4.271 + * This function is derived from PowerPC code (timebase clock frequency).
4.272 + * On MIPS it returns the number of timer ticks per second.
4.273 + */
4.274 +unsigned long get_tbclk (void)
4.275 +{
4.276 + return TIMER_HZ;
4.277 +}
4.278 +
4.279 +/* CPU-specific routines from U-Boot.
4.280 + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
4.281 + See: u-boot/arch/mips/include/asm/cacheops.h
4.282 +*/
4.283 +
4.284 +#define Index_Store_Tag_I 0x08
4.285 +#define Index_Writeback_Inv_D 0x15
4.286 +
4.287 +void flush_icache_all(void)
4.288 +{
4.289 + u32 addr, t = 0;
4.290 +
4.291 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
4.292 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
4.293 +
4.294 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
4.295 + addr += CONFIG_SYS_CACHELINE_SIZE) {
4.296 + asm volatile (
4.297 + ".set mips3\n\t"
4.298 + " cache %0, 0(%1)\n\t"
4.299 + ".set mips2\n\t"
4.300 + :
4.301 + : "I" (Index_Store_Tag_I), "r"(addr));
4.302 + }
4.303 +
4.304 + /* invalicate btb */
4.305 + asm volatile (
4.306 + ".set mips32\n\t"
4.307 + "mfc0 %0, $16, 7\n\t"
4.308 + "nop\n\t"
4.309 + "ori %0,2\n\t"
4.310 + "mtc0 %0, $16, 7\n\t"
4.311 + ".set mips2\n\t"
4.312 + :
4.313 + : "r" (t));
4.314 +}
4.315 +
4.316 +void flush_dcache_all(void)
4.317 +{
4.318 + u32 addr;
4.319 +
4.320 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
4.321 + addr += CONFIG_SYS_CACHELINE_SIZE) {
4.322 + asm volatile (
4.323 + ".set mips3\n\t"
4.324 + " cache %0, 0(%1)\n\t"
4.325 + ".set mips2\n\t"
4.326 + :
4.327 + : "I" (Index_Writeback_Inv_D), "r"(addr));
4.328 + }
4.329 +
4.330 + asm volatile ("sync");
4.331 +}
4.332 +
4.333 +void flush_cache_all(void)
4.334 +{
4.335 + flush_dcache_all();
4.336 + flush_icache_all();
4.337 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
5.2 +++ b/board-nanonote2.h Sun Jun 07 18:21:24 2015 +0200
5.3 @@ -0,0 +1,17 @@
5.4 +#ifndef __BOARD_NANONOTE2_H__
5.5 +#define __BOARD_NANONOTE2_H__
5.6 +
5.7 +/* Initialisation functions. */
5.8 +
5.9 +void gpio_init2(void);
5.10 +void cpm_init(void);
5.11 +void rtc_init(void);
5.12 +int timer_init(void);
5.13 +
5.14 +/* Utility functions. */
5.15 +
5.16 +void udelay(unsigned long usec);
5.17 +void flush_cache_all(void);
5.18 +unsigned long get_memory_size(void);
5.19 +
5.20 +#endif /* __BOARD_NANONOTE2_H__ */
6.1 --- a/head1.S Sun Jun 07 02:20:54 2015 +0200
6.2 +++ b/head1.S Sun Jun 07 18:21:24 2015 +0200
6.3 @@ -1,12 +1,12 @@
6.4 /*
6.5 - * head.S
6.6 - *
6.7 * Entry point of the firmware.
6.8 - * The firmware code are executed in the ICache.
6.9 + * The firmware code is executed in the ICache.
6.10 *
6.11 * Copyright 2009 (C) Qi Hardware Inc.,
6.12 * Author: Xiangfu Liu <xiangfu@sharism.cc>
6.13 *
6.14 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
6.15 + *
6.16 * This program is free software; you can redistribute it and/or
6.17 * modify it under the terms of the GNU General Public License
6.18 * version 3 as published by the Free Software Foundation.
6.19 @@ -39,8 +39,7 @@
6.20 .word 0x0
6.21 .word 0x0
6.22 .word 0x0
6.23 - /* reserve 8 words for args
6.24 - * this is must big then sizeof(sturct fw_args)
6.25 + /* reserve 8 words for args sizeof(struct fw_args)
6.26 */
6.27 real_start:
6.28 /*
7.1 --- a/head2.S Sun Jun 07 02:20:54 2015 +0200
7.2 +++ b/head2.S Sun Jun 07 18:21:24 2015 +0200
7.3 @@ -1,6 +1,4 @@
7.4 /*
7.5 - * head.S
7.6 - *
7.7 * Entry point of the firmware.
7.8 * The firmware code are executed in the ICache.
7.9 * Do not edit!
7.10 @@ -28,7 +26,7 @@
7.11 real_start:
7.12 /* setup stack, jump to C code */
7.13 add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0
7.14 - add $25, $20, 0x40 // t9 = usb_main()
7.15 + add $25, $20, 0x40 // t9 = c_main()
7.16 j $25
7.17 nop
7.18
8.1 --- a/lcd.c Sun Jun 07 02:20:54 2015 +0200
8.2 +++ b/lcd.c Sun Jun 07 18:21:24 2015 +0200
8.3 @@ -20,7 +20,7 @@
8.4
8.5 #include "xburst_types.h"
8.6 #include "nanonote_gpm940b0.h"
8.7 -#include "board-nanonote.h"
8.8 +#include "board-nanonote2.h"
8.9
8.10 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
8.11 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
9.1 --- a/nanonote_gpm940b0.c Sun Jun 07 02:20:54 2015 +0200
9.2 +++ b/nanonote_gpm940b0.c Sun Jun 07 18:21:24 2015 +0200
9.3 @@ -26,7 +26,7 @@
9.4
9.5 #include "jz4740.h"
9.6 #include "nanonote_gpm940b0.h"
9.7 -#include "board-nanonote.h"
9.8 +#include "board-nanonote2.h"
9.9
9.10 #define align2(n) (n)=((((n)+1)>>1)<<1)
9.11 #define align4(n) (n)=((((n)+3)>>2)<<2)
10.1 --- a/stage2.c Sun Jun 07 02:20:54 2015 +0200
10.2 +++ b/stage2.c Sun Jun 07 18:21:24 2015 +0200
10.3 @@ -18,12 +18,11 @@
10.4 * this program. If not, see <http://www.gnu.org/licenses/>.
10.5 */
10.6
10.7 -#include "board-nanonote.h"
10.8 +#include "board-nanonote2.h"
10.9 #include "lcd.h"
10.10
10.11 void c_main(void)
10.12 {
10.13 - load_args();
10.14 gpio_init2();
10.15 cpm_init();
10.16 rtc_init();