1.1 --- a/stage1/Makefile Tue Jun 09 21:26:39 2015 +0200
1.2 +++ b/stage1/Makefile Tue Jun 09 21:36:40 2015 +0200
1.3 @@ -42,8 +42,8 @@
1.4
1.5 # Ordering of objects is important and cannot be left to replacement rules.
1.6
1.7 -SRC = head1.S stage1.c board-nanonote.c
1.8 -OBJ = head1.o stage1.o board-nanonote.o
1.9 +SRC = head1.S stage1.c board.c
1.10 +OBJ = head1.o stage1.o board.o
1.11
1.12 .PHONY: all clean distclean
1.13
2.1 --- a/stage1/board-nanonote.c Tue Jun 09 21:26:39 2015 +0200
2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
2.3 @@ -1,226 +0,0 @@
2.4 -/*
2.5 - * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools.
2.6 - *
2.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
2.8 - * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
2.9 - * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
2.10 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
2.11 - *
2.12 - * This program is free software; you can redistribute it and/or modify it under
2.13 - * the terms of the GNU General Public License as published by the Free Software
2.14 - * Foundation; either version 3 of the License, or (at your option) any later
2.15 - * version.
2.16 - *
2.17 - * This program is distributed in the hope that it will be useful, but WITHOUT
2.18 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
2.19 - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
2.20 - * details.
2.21 - *
2.22 - * You should have received a copy of the GNU General Public License along with
2.23 - * this program. If not, see <http://www.gnu.org/licenses/>.
2.24 - */
2.25 -
2.26 -#include "jz4740.h"
2.27 -#include "sdram.h"
2.28 -#include "usb_boot_defines.h"
2.29 -
2.30 -/* These arguments are initialised by usbboot and are defined in...
2.31 - /etc/xburst-tools/usbboot.cfg. */
2.32 -
2.33 -struct fw_args *fw_args;
2.34 -volatile u32 FW_CPU_ID;
2.35 -volatile u8 FW_SDRAM_BW16;
2.36 -volatile u8 FW_SDRAM_BANK4;
2.37 -volatile u8 FW_SDRAM_ROW;
2.38 -volatile u8 FW_SDRAM_COL;
2.39 -volatile u8 FW_CONFIG_MOBILE_SDRAM;
2.40 -volatile u8 FW_IS_SHARE;
2.41 -
2.42 -void load_args(void)
2.43 -{
2.44 - /* Get the fw args from memory. See head1.S for the memory layout. */
2.45 -
2.46 - fw_args = (struct fw_args *)0x80002008;
2.47 - FW_CPU_ID = fw_args->cpu_id ;
2.48 - FW_SDRAM_BW16 = fw_args->bus_width;
2.49 - FW_SDRAM_BANK4 = fw_args->bank_num;
2.50 - FW_SDRAM_ROW = fw_args->row_addr;
2.51 - FW_SDRAM_COL = fw_args->col_addr;
2.52 - FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
2.53 - FW_IS_SHARE = fw_args->is_busshare;
2.54 -}
2.55 -
2.56 -/* Initialisation functions. */
2.57 -
2.58 -void gpio_init(void)
2.59 -{
2.60 - /*
2.61 - * Initialize NAND Flash Pins
2.62 - */
2.63 - __gpio_as_nand();
2.64 -
2.65 - /*
2.66 - * Initialize SDRAM pins
2.67 - */
2.68 - __gpio_as_sdram_16bit_4720();
2.69 -}
2.70 -
2.71 -void pll_init(void)
2.72 -{
2.73 - register unsigned int cfcr, plcr1;
2.74 - int nf, pllout2;
2.75 -
2.76 - /* See CPCCR (Clock Control Register).
2.77 - * 0 == same frequency; 2 == f/3
2.78 - */
2.79 -
2.80 - cfcr = CPM_CPCCR_CLKOEN |
2.81 - CPM_CPCCR_PCS |
2.82 - (0 << CPM_CPCCR_CDIV_BIT) |
2.83 - (2 << CPM_CPCCR_HDIV_BIT) |
2.84 - (2 << CPM_CPCCR_PDIV_BIT) |
2.85 - (2 << CPM_CPCCR_MDIV_BIT) |
2.86 - (2 << CPM_CPCCR_LDIV_BIT);
2.87 -
2.88 - /* Init USB Host clock.
2.89 - * Desired frequency == 48MHz
2.90 - */
2.91 -
2.92 -#ifdef CONFIG_CPU_JZ4730
2.93 - cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25);
2.94 -#else
2.95 - /* Determine the divider clock output based on the PCS bit. */
2.96 - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
2.97 -
2.98 - /* Divisor == UHCCDR + 1 */
2.99 - REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
2.100 -#endif
2.101 -
2.102 - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
2.103 - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
2.104 - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
2.105 - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
2.106 - CPM_CPPCR_PLLEN; /* enable PLL */
2.107 -
2.108 - /* Update PLL and wait. */
2.109 -
2.110 - REG_CPM_CPCCR = cfcr;
2.111 - REG_CPM_CPPCR = plcr1;
2.112 - while (!__cpm_pll_is_on());
2.113 -}
2.114 -
2.115 -void sdram_init(void)
2.116 -{
2.117 - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
2.118 - unsigned int pllout = __cpm_get_pllout();
2.119 -
2.120 - unsigned int cas_latency_sdmr[2] = {
2.121 - EMC_SDMR_CAS_2,
2.122 - EMC_SDMR_CAS_3,
2.123 - };
2.124 -
2.125 - unsigned int cas_latency_dmcr[2] = {
2.126 - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
2.127 - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
2.128 - };
2.129 -
2.130 - /* Divisors for CPCCR values. */
2.131 -
2.132 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
2.133 -
2.134 - cpu_clk = pllout / div[__cpm_get_cdiv()];
2.135 - mem_clk = pllout / div[__cpm_get_mdiv()];
2.136 -
2.137 - REG_EMC_BCR = 0; /* Disable bus release */
2.138 - REG_EMC_RTCSR = 0; /* Disable clock for counting */
2.139 -
2.140 - /* Fault DMCR value for mode register setting*/
2.141 - dmcr0 = (0<<EMC_DMCR_RA_BIT) |
2.142 - (0<<EMC_DMCR_CA_BIT) |
2.143 - (0<<EMC_DMCR_BA_BIT) |
2.144 - (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.145 - EMC_DMCR_EPIN |
2.146 - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
2.147 -
2.148 - /* Basic DMCR value */
2.149 - dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) |
2.150 - ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) |
2.151 - ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) |
2.152 - (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.153 - EMC_DMCR_EPIN |
2.154 - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
2.155 -
2.156 - /* SDRAM timimg */
2.157 - ns = 1000000000 / mem_clk;
2.158 - tmp = SDRAM_TRAS/ns;
2.159 - if (tmp < 4) tmp = 4;
2.160 - if (tmp > 11) tmp = 11;
2.161 - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
2.162 - tmp = SDRAM_RCD/ns;
2.163 - if (tmp > 3) tmp = 3;
2.164 - dmcr |= (tmp << EMC_DMCR_RCD_BIT);
2.165 - tmp = SDRAM_TPC/ns;
2.166 - if (tmp > 7) tmp = 7;
2.167 - dmcr |= (tmp << EMC_DMCR_TPC_BIT);
2.168 - tmp = SDRAM_TRWL/ns;
2.169 - if (tmp > 3) tmp = 3;
2.170 - dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
2.171 - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
2.172 - if (tmp > 14) tmp = 14;
2.173 - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
2.174 -
2.175 - /* SDRAM mode value */
2.176 - sdmode = EMC_SDMR_BT_SEQ |
2.177 - EMC_SDMR_OM_NORMAL |
2.178 - EMC_SDMR_BL_4 |
2.179 - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
2.180 -
2.181 - /* jz4730 additional measures */
2.182 -#ifdef CONFIG_CPU_JZ4730
2.183 - if (FW_SDRAM_BW16)
2.184 - sdmode <<= 1;
2.185 - else
2.186 - sdmode <<= 2;
2.187 -#endif
2.188 -
2.189 - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
2.190 - REG_EMC_DMCR = dmcr;
2.191 - REG8(EMC_SDMR0|sdmode) = 0;
2.192 -
2.193 - /* jz4730 additional measures */
2.194 -#ifdef CONFIG_CPU_JZ4730
2.195 - REG8(EMC_SDMR1|sdmode) = 0;
2.196 -#endif
2.197 -
2.198 - /* Wait for precharge, > 200us */
2.199 - tmp = (cpu_clk / 1000000) * 1000;
2.200 - while (tmp--);
2.201 -
2.202 - /* Stage 2. Enable auto-refresh */
2.203 - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
2.204 -
2.205 - tmp = SDRAM_TREF/ns;
2.206 - tmp = tmp/64 + 1;
2.207 - if (tmp > 0xff) tmp = 0xff;
2.208 - REG_EMC_RTCOR = tmp;
2.209 - REG_EMC_RTCNT = 0;
2.210 - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
2.211 -
2.212 - /* Wait for number of auto-refresh cycles */
2.213 - tmp = (cpu_clk / 1000000) * 1000;
2.214 - while (tmp--);
2.215 -
2.216 - /* Stage 3. Mode Register Set */
2.217 - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
2.218 - REG8(EMC_SDMR0|sdmode) = 0;
2.219 -
2.220 - /* jz4730 additional measures */
2.221 -#ifdef CONFIG_CPU_JZ4730
2.222 - REG8(EMC_SDMR1|sdmode) = 0;
2.223 -#endif
2.224 -
2.225 - /* Set back to basic DMCR value */
2.226 - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
2.227 -
2.228 - /* everything is ok now */
2.229 -}
3.1 --- a/stage1/board-nanonote.h Tue Jun 09 21:26:39 2015 +0200
3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
3.3 @@ -1,11 +0,0 @@
3.4 -#ifndef __BOARD_NANONOTE_H__
3.5 -#define __BOARD_NANONOTE_H__
3.6 -
3.7 -/* Initialisation functions. */
3.8 -
3.9 -void load_args(void);
3.10 -void gpio_init(void);
3.11 -void pll_init(void);
3.12 -void sdram_init(void);
3.13 -
3.14 -#endif /* __BOARD_NANONOTE_H__ */
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/stage1/board.c Tue Jun 09 21:36:40 2015 +0200
4.3 @@ -0,0 +1,231 @@
4.4 +/*
4.5 + * Generic board initialisation, based on uboot-xburst and xburst-tools.
4.6 + *
4.7 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4.8 + * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
4.9 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
4.10 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
4.11 + *
4.12 + * This program is free software; you can redistribute it and/or modify it under
4.13 + * the terms of the GNU General Public License as published by the Free Software
4.14 + * Foundation; either version 3 of the License, or (at your option) any later
4.15 + * version.
4.16 + *
4.17 + * This program is distributed in the hope that it will be useful, but WITHOUT
4.18 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
4.19 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
4.20 + * details.
4.21 + *
4.22 + * You should have received a copy of the GNU General Public License along with
4.23 + * this program. If not, see <http://www.gnu.org/licenses/>.
4.24 + */
4.25 +
4.26 +#ifdef CONFIG_CPU_JZ4730
4.27 +#include "jz4730.h"
4.28 +#else
4.29 +#include "jz4740.h"
4.30 +#endif
4.31 +
4.32 +#include "sdram.h"
4.33 +#include "usb_boot_defines.h"
4.34 +
4.35 +/* These arguments are initialised by usbboot and are defined in...
4.36 + /etc/xburst-tools/usbboot.cfg. */
4.37 +
4.38 +struct fw_args *fw_args;
4.39 +volatile u32 FW_CPU_ID;
4.40 +volatile u8 FW_SDRAM_BW16;
4.41 +volatile u8 FW_SDRAM_BANK4;
4.42 +volatile u8 FW_SDRAM_ROW;
4.43 +volatile u8 FW_SDRAM_COL;
4.44 +volatile u8 FW_CONFIG_MOBILE_SDRAM;
4.45 +volatile u8 FW_IS_SHARE;
4.46 +
4.47 +void load_args(void)
4.48 +{
4.49 + /* Get the fw args from memory. See head1.S for the memory layout. */
4.50 +
4.51 + fw_args = (struct fw_args *)0x80002008;
4.52 + FW_CPU_ID = fw_args->cpu_id ;
4.53 + FW_SDRAM_BW16 = fw_args->bus_width;
4.54 + FW_SDRAM_BANK4 = fw_args->bank_num;
4.55 + FW_SDRAM_ROW = fw_args->row_addr;
4.56 + FW_SDRAM_COL = fw_args->col_addr;
4.57 + FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
4.58 + FW_IS_SHARE = fw_args->is_busshare;
4.59 +}
4.60 +
4.61 +/* Initialisation functions. */
4.62 +
4.63 +void gpio_init(void)
4.64 +{
4.65 + /*
4.66 + * Initialize NAND Flash Pins
4.67 + */
4.68 + __gpio_as_nand();
4.69 +
4.70 + /*
4.71 + * Initialize SDRAM pins
4.72 + */
4.73 + __gpio_as_sdram_16bit_4720();
4.74 +}
4.75 +
4.76 +void pll_init(void)
4.77 +{
4.78 + register unsigned int cfcr, plcr1;
4.79 + int nf, pllout2;
4.80 +
4.81 + /* See CPCCR (Clock Control Register).
4.82 + * 0 == same frequency; 2 == f/3
4.83 + */
4.84 +
4.85 + cfcr = CPM_CPCCR_CLKOEN |
4.86 + CPM_CPCCR_PCS |
4.87 + (0 << CPM_CPCCR_CDIV_BIT) |
4.88 + (2 << CPM_CPCCR_HDIV_BIT) |
4.89 + (2 << CPM_CPCCR_PDIV_BIT) |
4.90 + (2 << CPM_CPCCR_MDIV_BIT) |
4.91 + (2 << CPM_CPCCR_LDIV_BIT);
4.92 +
4.93 + /* Init USB Host clock.
4.94 + * Desired frequency == 48MHz
4.95 + */
4.96 +
4.97 +#ifdef CONFIG_CPU_JZ4730
4.98 + cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25);
4.99 +#else
4.100 + /* Determine the divider clock output based on the PCS bit. */
4.101 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
4.102 +
4.103 + /* Divisor == UHCCDR + 1 */
4.104 + REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
4.105 +#endif
4.106 +
4.107 + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
4.108 + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
4.109 + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
4.110 + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
4.111 + CPM_CPPCR_PLLEN; /* enable PLL */
4.112 +
4.113 + /* Update PLL and wait. */
4.114 +
4.115 + REG_CPM_CPCCR = cfcr;
4.116 + REG_CPM_CPPCR = plcr1;
4.117 + while (!__cpm_pll_is_on());
4.118 +}
4.119 +
4.120 +void sdram_init(void)
4.121 +{
4.122 + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
4.123 + unsigned int pllout = __cpm_get_pllout();
4.124 +
4.125 + unsigned int cas_latency_sdmr[2] = {
4.126 + EMC_SDMR_CAS_2,
4.127 + EMC_SDMR_CAS_3,
4.128 + };
4.129 +
4.130 + unsigned int cas_latency_dmcr[2] = {
4.131 + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
4.132 + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
4.133 + };
4.134 +
4.135 + /* Divisors for CPCCR values. */
4.136 +
4.137 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
4.138 +
4.139 + cpu_clk = pllout / div[__cpm_get_cdiv()];
4.140 + mem_clk = pllout / div[__cpm_get_mdiv()];
4.141 +
4.142 + REG_EMC_BCR = 0; /* Disable bus release */
4.143 + REG_EMC_RTCSR = 0; /* Disable clock for counting */
4.144 +
4.145 + /* Fault DMCR value for mode register setting*/
4.146 + dmcr0 = (0<<EMC_DMCR_RA_BIT) |
4.147 + (0<<EMC_DMCR_CA_BIT) |
4.148 + (0<<EMC_DMCR_BA_BIT) |
4.149 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
4.150 + EMC_DMCR_EPIN |
4.151 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
4.152 +
4.153 + /* Basic DMCR value */
4.154 + dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) |
4.155 + ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) |
4.156 + ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) |
4.157 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
4.158 + EMC_DMCR_EPIN |
4.159 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
4.160 +
4.161 + /* SDRAM timimg */
4.162 + ns = 1000000000 / mem_clk;
4.163 + tmp = SDRAM_TRAS/ns;
4.164 + if (tmp < 4) tmp = 4;
4.165 + if (tmp > 11) tmp = 11;
4.166 + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
4.167 + tmp = SDRAM_RCD/ns;
4.168 + if (tmp > 3) tmp = 3;
4.169 + dmcr |= (tmp << EMC_DMCR_RCD_BIT);
4.170 + tmp = SDRAM_TPC/ns;
4.171 + if (tmp > 7) tmp = 7;
4.172 + dmcr |= (tmp << EMC_DMCR_TPC_BIT);
4.173 + tmp = SDRAM_TRWL/ns;
4.174 + if (tmp > 3) tmp = 3;
4.175 + dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
4.176 + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
4.177 + if (tmp > 14) tmp = 14;
4.178 + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
4.179 +
4.180 + /* SDRAM mode value */
4.181 + sdmode = EMC_SDMR_BT_SEQ |
4.182 + EMC_SDMR_OM_NORMAL |
4.183 + EMC_SDMR_BL_4 |
4.184 + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
4.185 +
4.186 + /* jz4730 additional measures */
4.187 +#ifdef CONFIG_CPU_JZ4730
4.188 + if (FW_SDRAM_BW16)
4.189 + sdmode <<= 1;
4.190 + else
4.191 + sdmode <<= 2;
4.192 +#endif
4.193 +
4.194 + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
4.195 + REG_EMC_DMCR = dmcr;
4.196 + REG8(EMC_SDMR0|sdmode) = 0;
4.197 +
4.198 + /* jz4730 additional measures */
4.199 +#ifdef CONFIG_CPU_JZ4730
4.200 + REG8(EMC_SDMR1|sdmode) = 0;
4.201 +#endif
4.202 +
4.203 + /* Wait for precharge, > 200us */
4.204 + tmp = (cpu_clk / 1000000) * 1000;
4.205 + while (tmp--);
4.206 +
4.207 + /* Stage 2. Enable auto-refresh */
4.208 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
4.209 +
4.210 + tmp = SDRAM_TREF/ns;
4.211 + tmp = tmp/64 + 1;
4.212 + if (tmp > 0xff) tmp = 0xff;
4.213 + REG_EMC_RTCOR = tmp;
4.214 + REG_EMC_RTCNT = 0;
4.215 + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
4.216 +
4.217 + /* Wait for number of auto-refresh cycles */
4.218 + tmp = (cpu_clk / 1000000) * 1000;
4.219 + while (tmp--);
4.220 +
4.221 + /* Stage 3. Mode Register Set */
4.222 + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
4.223 + REG8(EMC_SDMR0|sdmode) = 0;
4.224 +
4.225 + /* jz4730 additional measures */
4.226 +#ifdef CONFIG_CPU_JZ4730
4.227 + REG8(EMC_SDMR1|sdmode) = 0;
4.228 +#endif
4.229 +
4.230 + /* Set back to basic DMCR value */
4.231 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
4.232 +
4.233 + /* everything is ok now */
4.234 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
5.2 +++ b/stage1/board.h Tue Jun 09 21:36:40 2015 +0200
5.3 @@ -0,0 +1,11 @@
5.4 +#ifndef __BOARD_H__
5.5 +#define __BOARD_H__
5.6 +
5.7 +/* Initialisation functions. */
5.8 +
5.9 +void load_args(void);
5.10 +void gpio_init(void);
5.11 +void pll_init(void);
5.12 +void sdram_init(void);
5.13 +
5.14 +#endif /* __BOARD_H__ */
6.1 --- a/stage1/stage1.c Tue Jun 09 21:26:39 2015 +0200
6.2 +++ b/stage1/stage1.c Tue Jun 09 21:36:40 2015 +0200
6.3 @@ -18,7 +18,7 @@
6.4 * this program. If not, see <http://www.gnu.org/licenses/>.
6.5 */
6.6
6.7 -#include "board-nanonote.h"
6.8 +#include "board.h"
6.9
6.10 void c_main(void)
6.11 {