1.1 --- a/include/nanonote.h Mon Jun 08 19:20:02 2015 +0200
1.2 +++ b/include/nanonote.h Mon Jun 08 19:33:10 2015 +0200
1.3 @@ -53,6 +53,10 @@
1.4 #define SDRAM_TRWL 7 /* Write Latency Time */
1.5 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1.6
1.7 +#define SDRAM_ROW0 11 /* Row address minimum */
1.8 +#define SDRAM_COL0 8 /* Column address minimum */
1.9 +#define SDRAM_BANK40 0 /* Bank minimum */
1.10 +
1.11 /*
1.12 * Cache configuration
1.13 */
2.1 --- a/stage1/board-nanonote.c Mon Jun 08 19:20:02 2015 +0200
2.2 +++ b/stage1/board-nanonote.c Mon Jun 08 19:33:10 2015 +0200
2.3 @@ -132,21 +132,17 @@
2.4 REG_EMC_RTCSR = 0; /* Disable clock for counting */
2.5
2.6 /* Fault DMCR value for mode register setting*/
2.7 -#define SDRAM_ROW0 11
2.8 -#define SDRAM_COL0 8
2.9 -#define SDRAM_BANK40 0
2.10 -
2.11 - dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
2.12 - ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
2.13 - (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
2.14 + dmcr0 = (0<<EMC_DMCR_RA_BIT) |
2.15 + (0<<EMC_DMCR_CA_BIT) |
2.16 + (0<<EMC_DMCR_BA_BIT) |
2.17 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.18 EMC_DMCR_EPIN |
2.19 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
2.20
2.21 /* Basic DMCR value */
2.22 - dmcr = ((FW_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
2.23 - ((FW_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
2.24 - (FW_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
2.25 + dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) |
2.26 + ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) |
2.27 + ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) |
2.28 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
2.29 EMC_DMCR_EPIN |
2.30 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];