1.1 --- a/ULA.txt Fri Dec 31 15:11:32 2021 +0100
1.2 +++ b/ULA.txt Fri Dec 31 15:12:51 2021 +0100
1.3 @@ -223,7 +223,8 @@
1.4 access rate employed by the ULA does not involve the complete process for
1.5 accessing the RAM: upon setting up the address and issuing the ~RAS signal,
1.6 the ULA is able to make a pair of column accesses on the same "row" of memory,
1.7 -effectively achieving an average access rate of 4MHz.
1.8 +effectively achieving an average access rate of 4MHz in an 8-bit
1.9 +configuration.
1.10
1.11 However, if arbitrary pairs of column accesses were to be attempted, as would
1.12 be required by CPU and ULA interleaving, the ~RAS signal would need to be
1.13 @@ -231,6 +232,13 @@
1.14 access a memory location to beyond the period of a 4MHz cycle, making it
1.15 impossible to employ interleaved accesses at such a rate.
1.16
1.17 +In conclusion, a strict interleaving strategy is not possible, but by using
1.18 +pixel data buffering and employing two ULA accesses per 2MHz cycle to obtain
1.19 +two bytes in that cycle, each adjacent 2MHz cycle can be given to the CPU,
1.20 +thus achieving an effective throughput during display update periods of 3
1.21 +bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and
1.22 +thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM.
1.23 +
1.24 CPU Clock Notes
1.25 ---------------
1.26