1.1 --- a/ULA.txt Fri Feb 22 16:05:35 2019 +0100
1.2 +++ b/ULA.txt Sun Feb 24 01:55:30 2019 +0100
1.3 @@ -42,11 +42,12 @@
1.4 of the 2MHz clock to complete each access operation. Since the CPU and ULA
1.5 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
1.6 effectively run at 1MHz (since every other 500ns period involves the ULA
1.7 -accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
1.8 -frequency is divided by the ULA (IC1) depending on the screen mode in use.
1.9 +accessing RAM) during transfers of screen data.
1.10
1.11 -Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.12 -patterns corresponding to 16MHz cycles are required:
1.13 +The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
1.14 +by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
1.15 +approximately 62.5ns. To access the memory, the following patterns
1.16 +corresponding to 16MHz cycles are required:
1.17
1.18 Time (ns): 0-------------- 500------------- ...
1.19 2 MHz cycle: 0 1 ...
1.20 @@ -116,7 +117,7 @@
1.21
1.22 See: Acorn Electron Advanced User Guide
1.23 See: Acorn Electron Service Manual
1.24 - http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.25 + http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.26 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.27 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
1.28
1.29 @@ -622,6 +623,9 @@
1.30 MODE 4, 5 19968 bytes 29696 bytes
1.31 MODE 6 19968 bytes 32256 bytes
1.32
1.33 +(Here, the uncontended 2MHz bandwidth for a display period would be 39936
1.34 +bytes, being 128 cycles per line over 312 lines.)
1.35 +
1.36 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
1.37 because all access opportunities to RAM are doubled. Meanwhile, in the other
1.38 modes, some CPU accesses occur alongside ULA accesses and thus cannot be