1.1 --- a/ula.py Sun Feb 26 23:11:44 2012 +0100
1.2 +++ b/ula.py Sun Feb 26 23:12:35 2012 +0100
1.3 @@ -152,6 +152,11 @@
1.4
1.5 "Reset the ULA."
1.6
1.7 + # General state.
1.8 +
1.9 + self.nmi = 0 # no NMI asserted initially
1.10 + self.irq_vsync = 0 # no IRQ asserted initially
1.11 +
1.12 # Internal state.
1.13
1.14 self.cycle = 0 # counter within each 2MHz period
1.15 @@ -302,7 +307,7 @@
1.16
1.17 # Clock management.
1.18
1.19 - access_ram = self.access == 0 and self.read_pixels() and not self.ssub
1.20 + access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
1.21
1.22 # Set row address (for ULA access only).
1.23
1.24 @@ -411,6 +416,9 @@
1.25 self.hsync()
1.26 if self.y == 0:
1.27 self.vsync()
1.28 + self.irq_vsync = 0
1.29 + elif self.y == MAX_PIXELLINE:
1.30 + self.irq_vsync = 1
1.31
1.32 # Detect the end of hsync.
1.33