1.1 --- a/ULA.txt Tue Nov 26 15:38:07 2019 +0100
1.2 +++ b/ULA.txt Tue Apr 07 21:31:19 2020 +0200
1.3 @@ -640,14 +640,14 @@
1.4
1.5 This would improve CPU bandwidth as follows:
1.6
1.7 - Standard ULA Enhanced ULA
1.8 -MODE 0, 1, 2 9728 bytes 19456 bytes
1.9 -MODE 3 12288 bytes 24576 bytes
1.10 -MODE 4, 5 19968 bytes 29696 bytes
1.11 -MODE 6 19968 bytes 32256 bytes
1.12 + Standard ULA Enhanced ULA % Total Bandwidth Speedup
1.13 +MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
1.14 +MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
1.15 +MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
1.16 +MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
1.17
1.18 -(Here, the uncontended 2MHz bandwidth for a display period would be 39936
1.19 -bytes, being 128 cycles per line over 312 lines.)
1.20 +(Here, the uncontended total 2MHz bandwidth for a display period would be
1.21 +39936 bytes, being 128 cycles per line over 312 lines.)
1.22
1.23 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
1.24 because all access opportunities to RAM are doubled. Meanwhile, in the other
1.25 @@ -656,7 +656,12 @@
1.26
1.27 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
1.28 within the time constraints of 2MHz operation. There is no time remaining in a
1.29 -2MHz cycle for the CPU to receive and process any retrieved data.
1.30 +2MHz cycle for the CPU to receive and process any retrieved data once the
1.31 +necessary signalling has been performed. The only way for the CPU to be able
1.32 +to access the RAM quickly enough would be to do away with the double 4-bit
1.33 +access mechanism and to have a single 8-bit channel to the memory. This would
1.34 +require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
1.35 +would also potentially simplify the ULA.
1.36
1.37 Enhancement: Region Blanking
1.38 ----------------------------