1.1 --- a/ULA.txt Fri Feb 03 00:21:28 2012 +0100
1.2 +++ b/ULA.txt Thu Feb 09 00:14:22 2012 +0100
1.3 @@ -30,14 +30,20 @@
1.4 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.5 ~RAS: 0 1 0 1 ...
1.6 ~CAS: 0 1 0 1 0 1 0 1 ...
1.7 - A B
1.8 - F S
1.9 + A B B A B B
1.10 + F S F S
1.11
1.12 Here, "A" indicates the row and column addresses being latched into the RAM
1.13 -(on a negative edge for RAS and CAS respectively), and "B" indicates the
1.14 +(on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
1.15 second column address being latched into the RAM. Presumably, the first and
1.16 second half-bytes can be read at "F" and "S" respectively.
1.17
1.18 +Note that the Service Manual refers to the negative edge of RAS and CAS, but
1.19 +the datasheet for the similar TM4164EC4 product shows latching on the negative
1.20 +edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
1.21 +communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
1.22 +"page mode" provides the appropriate behaviour for that particular product.
1.23 +
1.24 Shadow/Expanded Memory
1.25 ----------------------
1.26
1.27 @@ -408,9 +414,11 @@
1.28
1.29 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1.30
1.31 - RAS (row address strobe setting the row address on a negative edge)
1.32 + RAS (row address strobe setting the row address on a negative edge - see the
1.33 + timing notes)
1.34
1.35 - CAS (column address strobe setting the column address on a negative edge)
1.36 + CAS (column address strobe setting the column address on a negative edge -
1.37 + see the timing notes)
1.38
1.39 WE (sets write enable with logic 0, read with logic 1)
1.40