1.1 --- a/ULA.txt Fri Feb 10 01:07:20 2012 +0100
1.2 +++ b/ULA.txt Mon Feb 13 22:00:09 2012 +0100
1.3 @@ -1,16 +1,13 @@
1.4 Timing
1.5 ------
1.6
1.7 -According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
1.8 -which are used to generate pixel data. At 50Hz, this means that 128 cycles are
1.9 -spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles / 312
1.10 -~= 128 cycles). This is consistent with the observation that each scanline
1.11 +According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
1.12 +of which are used to generate pixel data. At 50Hz, this means that 128 cycles
1.13 +are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
1.14 +312 ~= 128 cycles). This is consistent with the observation that each scanline
1.15 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
1.16 out of 64 microseconds in each scanline.
1.17
1.18 -See: Acorn Electron Advanced User Guide
1.19 -See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.20 -
1.21 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
1.22 each providing two bits of each byte) using two cycles within the 500ns period
1.23 of the 2MHz clock to complete each access operation. Since the CPU and ULA
1.24 @@ -19,9 +16,6 @@
1.25 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
1.26 frequency is divided by the ULA (IC1) depending on the screen mode in use.
1.27
1.28 -See: Acorn Electron Service Manual
1.29 - http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.30 -
1.31 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.32 patterns corresponding to 16MHz cycles are required:
1.33
1.34 @@ -47,11 +41,84 @@
1.35 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
1.36 "page mode" provides the appropriate behaviour for that particular product.
1.37
1.38 -See: http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
1.39 +Video Timing
1.40 +------------
1.41 +
1.42 +According to 8.7 in the Service Manual, and the PAL Wikipedia page,
1.43 +approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
1.44 +(including the "colour burst"), and 1.65µs for the "front porch", totalling
1.45 +12.05µs and thus leaving 51.95µs for the active video signal for each
1.46 +scanline. As the Service Manual suggests in the oscilloscope traces, the
1.47 +display information is transmitted more or less centred within the active
1.48 +video period since the ULA will only be providing pixel data for 40µs in each
1.49 +scanline.
1.50
1.51 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
1.52 each scanline can be divided into 1024 cycles, although only 640 at most are
1.53 -actively used to provide pixel data.
1.54 +actively used to provide pixel data. Pixel data production should only occur
1.55 +within a certain period on each scanline, approximately 262 cycles after the
1.56 +start of hsync:
1.57 +
1.58 + active video period = 51.95µs
1.59 + pixel data period = 40µs
1.60 + total silent period = 51.95µs - 40µs = 11.95µs
1.61 + silent periods (before and after) = 11.95µs / 2 = 5.975µs
1.62 + hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
1.63 + time before pixel data period = 10.4µs + 5.975µs = 16.375µs
1.64 + pixel data period start cycle = 16.375µs / 62.5ns = 262
1.65 +
1.66 +By choosing a number divisible by 8, the RAM access mechanism can be
1.67 +synchronised with the pixel production. Thus, 264 is a more appropriate start
1.68 +cycle.
1.69 +
1.70 +The "vertical blanking period", meaning the period before picture information
1.71 +in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
1.72 +1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
1.73 +for 2.5 lines. Thus, the first visible scanline on the first field of a frame
1.74 +occurs half way through the 23rd scanline period measured from the start of
1.75 +vsync:
1.76 +
1.77 + 10 20 23
1.78 + Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
1.79 + Line from 1: 0 22 3
1.80 + Line on screen: .:::::VVVVV::::: 12233445566
1.81 + |_________________________________________________|
1.82 + 25 line vertical blanking period
1.83 +
1.84 +In the second field of a frame, the first visible scanline coincides with the
1.85 +24th scanline period measured from the start of line 313 in the frame:
1.86 +
1.87 + 310 336
1.88 + Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
1.89 + Line from 313: 0 23
1.90 + Line on screen: 88:::::VVVVV:::: 11223344
1.91 + 288 | |
1.92 + |_________________________________________________|
1.93 + 25 line vertical blanking period
1.94 +
1.95 +In order to consider only full lines, we might consider the start of each
1.96 +frame to occur 23 lines after the start of vsync.
1.97 +
1.98 +Again, it is likely that pixel data production should only occur on scanlines
1.99 +within a certain period on each frame. The "625/50" document indicates that
1.100 +only a certain region is "safe" to use, suggesting a vertically centred region
1.101 +with approximately 15 blank lines above and below the picture. Thus, the start
1.102 +of the picture could be chosen as 38 lines after the start of vsync.
1.103 +
1.104 +See: Acorn Electron Advanced User Guide
1.105 +See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.106 +See: http://en.wikipedia.org/wiki/PAL
1.107 +See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
1.108 +See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
1.109 + http://lipas.uwasa.fi/~f76998/video/modes/
1.110 +See: PAL TV timing and voltages
1.111 + http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
1.112 +See: Line Standards
1.113 + http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
1.114 +See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
1.115 + http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
1.116 +See: Acorn Electron Service Manual
1.117 + http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.118
1.119 Shadow/Expanded Memory
1.120 ----------------------