1.1 --- a/ULA.txt Thu Feb 09 00:14:22 2012 +0100
1.2 +++ b/ULA.txt Fri Feb 10 01:07:20 2012 +0100
1.3 @@ -3,8 +3,8 @@
1.4
1.5 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
1.6 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
1.7 -used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
1.8 -312 ~= 128 cycles). This is consistent with the observation that each scanline
1.9 +spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles / 312
1.10 +~= 128 cycles). This is consistent with the observation that each scanline
1.11 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
1.12 out of 64 microseconds in each scanline.
1.13
1.14 @@ -25,18 +25,21 @@
1.15 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.16 patterns corresponding to 16MHz cycles are required:
1.17
1.18 - Time (ns): 0-------------- 500------------
1.19 + Time (ns): 0-------------- 500------------ ...
1.20 2 MHz cycle: 0 1 ...
1.21 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.22 - ~RAS: 0 1 0 1 ...
1.23 - ~CAS: 0 1 0 1 0 1 0 1 ...
1.24 - A B B A B B
1.25 - F S F S
1.26 + ~RAS: 0 1 0 1 ...
1.27 + ~CAS: 0 1 0 1 0 1 0 1 ...
1.28 + A B B A B B ...
1.29 + F S F S ...
1.30 + a b b a b b ...
1.31
1.32 Here, "A" indicates the row and column addresses being latched into the RAM
1.33 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
1.34 second column address being latched into the RAM. Presumably, the first and
1.35 -second half-bytes can be read at "F" and "S" respectively.
1.36 +second half-bytes can be read at "F" and "S" respectively, and the row and
1.37 +column addresses must be made available at "a" and "b" respectively at the
1.38 +latest.
1.39
1.40 Note that the Service Manual refers to the negative edge of RAS and CAS, but
1.41 the datasheet for the similar TM4164EC4 product shows latching on the negative
1.42 @@ -44,6 +47,12 @@
1.43 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
1.44 "page mode" provides the appropriate behaviour for that particular product.
1.45
1.46 +See: http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
1.47 +
1.48 +Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
1.49 +each scanline can be divided into 1024 cycles, although only 640 at most are
1.50 +actively used to provide pixel data.
1.51 +
1.52 Shadow/Expanded Memory
1.53 ----------------------
1.54