1 #!/usr/bin/env python 2 3 """ 4 Acorn Electron ULA simulation. 5 6 Copyright (C) 2011, 2012, 2013, 2014, 2016 Paul Boddie <paul@boddie.org.uk> 7 8 This program is free software; you can redistribute it and/or modify it under 9 the terms of the GNU General Public License as published by the Free Software 10 Foundation; either version 3 of the License, or (at your option) any later 11 version. 12 13 This program is distributed in the hope that it will be useful, but WITHOUT ANY 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License along 18 with this program. If not, see <http://www.gnu.org/licenses/>. 19 """ 20 21 from array import array 22 from itertools import repeat 23 24 LINES_PER_ROW = 8 # the number of pixel lines per character row 25 MAX_HEIGHT = 256 # the height of the screen in pixels 26 MAX_WIDTH = 640 # the width of the screen in pixels 27 28 MAX_CSYNC = 2 # the scanline during which vsync ends 29 MIN_PIXELLINE = 28 # the first scanline involving pixel generation 30 MAX_SCANLINE = 312 # the number of scanlines in each frame 31 32 MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT 33 34 MAX_HSYNC = 64 # the number of cycles in each hsync period 35 MIN_PIXELPOS = 256 # the first cycle involving pixel generation 36 MAX_SCANPOS = 1024 # the number of cycles in each scanline 37 38 MAX_PIXELPOS = MIN_PIXELPOS + MAX_WIDTH 39 40 SCREEN_LIMIT = 0x8000 # the first address after the screen memory 41 MAX_MEMORY = 0x10000 # the number of addressable memory locations 42 MAX_RAM = 0x10000 # the number of addressable RAM locations (64Kb in each IC) 43 BLANK = (0, 0, 0) 44 45 def update(ula): 46 47 """ 48 Update the 'ula' for one frame. Return the resulting screen. 49 """ 50 51 video = ula.video 52 53 i = 0 54 limit = MAX_SCANLINE * MAX_SCANPOS 55 while i < limit: 56 ula.posedge() 57 video.update() 58 ula.negedge() 59 i += 1 60 61 return video.screen 62 63 class Video: 64 65 """ 66 A class representing the video circuitry. 67 """ 68 69 def __init__(self): 70 self.screen = array("B", repeat(0, MAX_WIDTH * 3 * MAX_HEIGHT)) 71 self.colour = BLANK 72 self.csync = 1 73 self.hs = 1 74 self.x = 0 75 self.y = 0 76 77 def set_csync(self, value): 78 if self.csync and not value: 79 self.y = 0 80 self.pos = 0 81 self.csync = value 82 83 def set_hs(self, value): 84 if self.hs and not value: 85 self.x = 0 86 self.y += 1 87 self.hs = value 88 89 def update(self): 90 if MIN_PIXELLINE <= self.y < MAX_PIXELLINE: 91 if MIN_PIXELPOS + 8 <= self.x < MAX_PIXELPOS + 8: 92 self.screen[self.pos] = self.colour[0]; self.pos += 1 93 self.screen[self.pos] = self.colour[1]; self.pos += 1 94 self.screen[self.pos] = self.colour[2]; self.pos += 1 95 self.x += 1 96 97 class RAM: 98 99 """ 100 A class representing the RAM circuits (IC4 to IC7). Each circuit 101 traditionally holds 64 kilobits, with each access obtaining 1 bit from each 102 IC, and thus two accesses being required to obtain a whole byte. Here, we 103 model the circuits with a list of 65536 half-bytes with each bit in a 104 half-byte representing a bit stored on a separate IC. 105 """ 106 107 def __init__(self): 108 109 "Initialise the RAM circuits." 110 111 self.memory = [0] * MAX_RAM 112 self.row_address = 0 113 self.column_address = 0 114 self.data = 0 115 self.read_not_write = 1 116 117 def row_select(self, address): 118 119 "The operation of asserting a row 'address' via RA0...RA7." 120 121 self.row_address = address 122 123 def row_deselect(self): 124 pass 125 126 def column_select(self, address): 127 128 "The operation of asserting a column 'address' via RA0...RA7." 129 130 self.column_address = address 131 132 # Read the data. 133 134 if self.read_not_write: 135 self.data = self.memory[self.row_address << 8 | self.column_address] 136 else: 137 self.memory[self.row_address << 8 | self.column_address] = self.data 138 139 def column_deselect(self): 140 pass 141 142 def read_select(self): 143 self.read_not_write = 1 144 145 def write_select(self): 146 self.read_not_write = 0 147 148 # Convenience methods. 149 150 def fill(self, start, end, value): 151 for i in xrange(start, end): 152 self.memory[i << 1] = value >> 4 153 self.memory[i << 1 | 0x1] = value & 0xf 154 155 class CPU: 156 157 "A CPU abstraction." 158 159 def __init__(self): 160 self.address = 0x1000 161 self.read_not_write = 1 162 163 class ULA: 164 165 """ 166 A class providing the ULA functionality. Instances of this class refer to 167 the system memory, maintain internal state (such as information about the 168 current screen mode), and provide outputs (such as the current pixel 169 colour). 170 """ 171 172 modes = [ 173 (640, 1, 32), (320, 2, 32), (160, 4, 32), # (width, depth, rows) 174 (640, 1, 25), (320, 1, 32), (160, 2, 32), 175 (320, 1, 25) 176 ] 177 178 def __init__(self, cpu, ram, video): 179 180 "Initialise the ULA with the given 'cpu', 'ram' and 'video' instances." 181 182 self.cpu = cpu 183 self.ram = ram 184 self.video = video 185 self.set_mode(6) 186 self.palette = map(get_physical_colour, range(0, 8) * 2) 187 188 self.reset() 189 190 def reset(self): 191 192 "Reset the ULA." 193 194 # General state. 195 196 self.nmi = 0 # no NMI asserted initially 197 self.irq_vsync = 0 # no IRQ asserted initially 198 self.cpu_clock = 0 # drive the CPU clock low 199 200 # Communication. 201 202 self.ram_address = 0 # address given to the RAM via RA0...RA7 203 self.data = 0 # data read from the RAM via RAM0...RAM3 204 self.cpu_address = 0 # address selected by the CPU via A0...A15 205 self.cpu_read = 0 # data read/write by the CPU selected using R/W 206 207 # Internal state. 208 209 self.access = 0 # counter used to determine whether a byte needs reading 210 self.have_pixels = 0 # whether pixel data has been read 211 self.pdata = 0 # decoded RAM data for pixel output 212 self.cycle = 1 # 8-state counter within each 2MHz period 213 self.pcycle = 0 # 8/4/2-state pixel output counter 214 215 self.next_frame() 216 217 def set_mode(self, mode): 218 219 """ 220 For the given 'mode', initialise the... 221 222 * width in pixels 223 * colour depth in bits per pixel 224 * number of character rows 225 * character row size in bytes 226 * screen size in bytes 227 * default screen start address 228 * horizontal pixel scaling factor 229 * row height in pixels 230 * display height in pixels 231 232 The ULA should be reset after a mode switch in order to cleanly display 233 a full screen. 234 """ 235 236 self.width, self.depth, rows = self.modes[mode] 237 238 columns = (self.width * self.depth) / 8 # bits read -> bytes read 239 self.access_frequency = 80 / columns # cycle frequency for reading bytes 240 row_size = columns * LINES_PER_ROW 241 242 # Memory access configuration. 243 # Note the limitation on positioning the screen start. 244 245 screen_size = row_size * rows 246 self.screen_start = (SCREEN_LIMIT - screen_size) & 0xff00 247 self.screen_size = SCREEN_LIMIT - self.screen_start 248 249 # Scanline configuration. 250 251 self.xscale = MAX_WIDTH / self.width # pixel width in display pixels 252 self.row_height = MAX_HEIGHT / rows # row height in display pixels 253 self.display_height = rows * self.row_height # display height in pixels 254 255 def vsync(self, value=0): 256 257 "Signal the start of a frame." 258 259 self.csync = value 260 self.video.set_csync(value) 261 262 def hsync(self, value=0): 263 264 "Signal the end of a scanline." 265 266 self.hs = value 267 self.video.set_hs(value) 268 269 def next_frame(self): 270 271 "Signal the start of a frame." 272 273 self.line_start = self.pixel_address = self.screen_start 274 self.line = self.line_start % LINES_PER_ROW 275 self.y = 0 276 self.x = 0 277 278 def next_horizontal(self): 279 280 "Visit the next horizontal position." 281 282 self.pixel_address += LINES_PER_ROW 283 self.wrap_address() 284 285 def next_vertical(self): 286 287 "Reset horizontal state within the active region of the frame." 288 289 self.y += 1 290 self.x = 0 291 292 if self.inside_frame(): 293 self.line += 1 294 295 # At the end of a row... 296 297 if self.line == self.row_height: 298 299 # After the end of the last line in a row, the address should already 300 # have been positioned on the last line of the next column. 301 302 self.pixel_address -= LINES_PER_ROW - 1 303 self.wrap_address() 304 self.line = 0 305 306 # Record the position of the start of the pixel row. 307 308 self.line_start = self.pixel_address 309 310 # Before any spacing between character rows... 311 312 elif self.in_line(): 313 314 # If not on a row boundary, move to the next line. Here, the address 315 # needs bringing back to the previous character row. 316 317 self.pixel_address = self.line_start + 1 318 self.wrap_address() 319 320 # Record the position of the start of the pixel row. 321 322 self.line_start = self.pixel_address 323 324 def in_line(self): return self.line < LINES_PER_ROW 325 def in_frame(self): return MIN_PIXELLINE <= self.y < (MIN_PIXELLINE + self.display_height) 326 def inside_frame(self): return MIN_PIXELLINE < self.y < (MIN_PIXELLINE + self.display_height) 327 def read_pixels(self): return MIN_PIXELPOS <= self.x < MAX_PIXELPOS and self.in_frame() 328 def write_pixels(self): return self.pcycle != 0 329 def next_pixel(self): return self.xscale == 1 or (self.xscale == 2 and self.cycle & 0b10101010) or (self.xscale == 4 and self.cycle & 0b10001000) 330 331 def posedge(self): 332 333 """ 334 Update the state of the ULA for each clock cycle. This involves updating 335 the pixel colour by reading from the pixel buffer. 336 """ 337 338 # Video signalling. 339 340 # Detect the end of the scanline. 341 342 if self.x == MAX_SCANPOS: 343 self.next_vertical() 344 345 # Detect the end of the frame. 346 347 if self.y == MAX_SCANLINE: 348 self.next_frame() 349 350 351 352 # Detect any sync conditions. 353 354 if self.x == 0: 355 self.hsync() 356 if self.y == 0: 357 self.vsync() 358 self.irq_vsync = 0 359 elif self.y == MAX_PIXELLINE: 360 self.irq_vsync = 1 361 362 # Detect the end of hsync. 363 364 elif self.x == MAX_HSYNC: 365 self.hsync(1) 366 367 # Detect the end of vsync. 368 369 elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2: 370 self.vsync(1) 371 372 373 374 # Clock management. 375 376 would_access_ram = self.access == 0 and self.read_pixels() and self.in_line() 377 access_ram = not self.nmi and would_access_ram 378 379 # Set row address (for ULA access only). 380 381 if self.cycle == 1: 382 383 # Either assert a required address or propagate the CPU address. 384 385 if access_ram: 386 self.init_row_address(self.pixel_address) 387 else: 388 self.init_row_address(self.cpu_address) 389 390 # Latch row address, set column address (for ULA access only). 391 392 elif self.cycle == 2: 393 394 # Select an address needed by the ULA or CPU. 395 396 self.ram.row_select(self.ram_address) 397 398 # Either assert a required address or propagate the CPU address. 399 400 if access_ram: 401 self.init_column_address(self.pixel_address, 0) 402 else: 403 self.init_column_address(self.cpu_address, 0) 404 405 # Latch column address. 406 407 elif self.cycle == 4: 408 409 # Select an address needed by the ULA or CPU. 410 411 self.ram.column_select(self.ram_address) 412 413 # Assert the RAM write enable if appropriate. 414 415 if access_ram: 416 self.ram.read_select() 417 else: 418 self.cpu_transfer_select() 419 420 # Read 4 bits (for ULA access only). 421 422 elif self.cycle == 8: 423 424 # Either read from a required address or transfer CPU data. 425 426 if access_ram: 427 self.data = self.ram.data << 4 428 else: 429 self.cpu_transfer_high() 430 431 # Set column address (for ULA access only). 432 433 elif self.cycle == 16: 434 self.ram.column_deselect() 435 436 # Either assert a required address or propagate the CPU address. 437 438 if access_ram: 439 self.init_column_address(self.pixel_address, 1) 440 else: 441 self.init_column_address(self.cpu_address, 1) 442 443 # Latch column address. 444 445 elif self.cycle == 32: 446 447 # Select an address needed by the ULA or CPU. 448 449 self.ram.column_select(self.ram_address) 450 451 # Read 4 bits (for ULA access only). 452 453 elif self.cycle == 64: 454 455 # Either read from a required address or transfer CPU data. 456 457 if access_ram: 458 self.data = self.data | self.ram.data 459 self.have_pixels = 1 460 else: 461 self.cpu_transfer_low() 462 463 # Advance to the next column even if an NMI is asserted. 464 465 if would_access_ram: 466 self.next_horizontal() 467 468 # Reset addresses. 469 470 elif self.cycle == 128: 471 self.ram.column_deselect() 472 self.ram.row_deselect() 473 474 # Update the RAM access controller. 475 476 self.access = (self.access + 1) % self.access_frequency 477 478 # Read the CPU address, if appropriate. 479 480 if not access_ram: 481 self.cpu_update_clock() 482 483 484 485 # Pixel production. 486 487 # For pixels within the frame, obtain and output the value. 488 489 if self.write_pixels(): 490 self.output_colour_value() 491 492 # Scale pixels horizontally, only accessing the next pixel value 493 # after the required number of scan positions. 494 495 if self.next_pixel(): 496 self.next_pixel_value() 497 498 # Detect spacing between character rows. 499 500 else: 501 self.video.colour = BLANK 502 503 def negedge(self): 504 505 "Update the state of the device." 506 507 # Initialise the pixel buffer if appropriate. Output starts after 508 # this cycle. 509 510 if self.cycle == 128 and self.have_pixels: 511 self.pdata = decode(self.data, self.depth) 512 self.pcycle = 1 513 self.have_pixels = 0 514 515 # Start a new cycle. 516 517 self.cycle = rotate(self.cycle, 1) 518 self.x += 1 519 520 def output_colour_value(self): 521 522 """ 523 Output the colour value for the current pixel by translating memory 524 content for the current mode. 525 """ 526 527 value = value_of_bits(self.pdata, self.depth) 528 self.video.colour = self.palette[value] 529 530 def next_pixel_value(self): 531 self.pdata = rotate(self.pdata, self.depth) 532 self.pcycle = rotate(self.pcycle, self.depth, zero=True) 533 534 def wrap_address(self): 535 if self.pixel_address >= SCREEN_LIMIT: 536 self.pixel_address -= self.screen_size 537 538 def init_row_address(self, address): 539 self.ram_address = (address & 0xff80) >> 7 540 541 def init_column_address(self, address, offset): 542 self.ram_address = (address & 0x7f) << 1 | offset 543 544 def cpu_transfer_high(self): 545 if self.cpu_read: 546 self.cpu_data = self.ram.data << 4 547 else: 548 self.ram.data = self.cpu_data >> 4 549 550 def cpu_transfer_low(self): 551 if self.cpu_read: 552 self.cpu_data = self.data | self.ram.data 553 else: 554 self.ram.data = self.cpu_data & 0b00001111 555 556 def cpu_read_address(self): 557 self.cpu_address = self.cpu.address 558 559 def cpu_transfer_data(self): 560 if self.cpu_read: 561 self.cpu.data = self.cpu_data 562 else: 563 self.cpu_data = self.cpu.data 564 565 def cpu_update_clock(self): 566 self.cpu_clock = not self.cpu_clock 567 if self.cpu_clock: 568 self.cpu_transfer_data() 569 else: 570 self.cpu_read_address() 571 572 def cpu_transfer_select(self): 573 self.cpu_read = self.cpu.read_not_write 574 if self.cpu_read: 575 self.ram.read_select() 576 else: 577 self.ram.write_select() 578 579 def rotate(value, depth, width=8, zero=False): 580 581 """ 582 Return 'value' rotated left by the number of bits given by 'depth', doing so 583 within a value 'width' given in bits. If 'zero' is true, rotate zero bits 584 into the lower bits when rotating. 585 """ 586 587 field = width - depth 588 top = value >> field 589 mask = 2 ** (width - depth) - 1 590 rest = value & mask 591 return (rest << depth) | (not zero and top or 0) 592 593 def value_of_bits(value, depth): 594 595 """ 596 Convert the upper bits of 'value' to a result, using 'depth' to indicate the 597 number of bits involved. 598 """ 599 600 return value >> (8 - depth) 601 602 def get_physical_colour(value): 603 604 """ 605 Return the physical colour as an RGB triple for the given 'value'. 606 """ 607 608 return value & 1, value >> 1 & 1, value >> 2 & 1 609 610 def decode(value, depth): 611 612 """ 613 Decode the given byte 'value' according to the 'depth' in bits per pixel, 614 returning a sequence of pixel values. 615 """ 616 617 if depth == 1: 618 return value 619 elif depth == 2: 620 return ((value & 128) | ((value & 8) << 3) | ((value & 64) >> 1) | ((value & 4) << 2) | 621 ((value & 32) >> 2) | ((value & 2) << 1) | ((value & 16) >> 3) | (value & 1)) 622 elif depth == 4: 623 return ((value & 128) | ((value & 32) << 1) | ((value & 8) << 2) | ((value & 2) << 3) | 624 ((value & 64) >> 3) | ((value & 16) >> 2) | ((value & 4) >> 1) | (value & 1)) 625 else: 626 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 627 628 # Convenience functions. 629 630 def encode(values, depth): 631 632 """ 633 Encode the given 'values' according to the 'depth' in bits per pixel, 634 returning a byte value for the pixels. 635 """ 636 637 result = 0 638 639 if depth == 1: 640 for value in values: 641 result = result << 1 | (value & 1) 642 elif depth == 2: 643 for value in values: 644 result = result << 1 | (value & 2) << 3 | (value & 1) 645 elif depth == 4: 646 for value in values: 647 result = result << 1 | (value & 8) << 3 | (value & 4) << 2 | (value & 2) << 1 | (value & 1) 648 else: 649 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 650 651 return result 652 653 def get_ula(): 654 655 "Return a ULA initialised with a memory array and video." 656 657 return ULA(get_cpu(), get_ram(), get_video()) 658 659 def get_video(): 660 661 "Return a video circuit." 662 663 return Video() 664 665 def get_ram(): 666 667 "Return an instance representing the computer's RAM hardware." 668 669 return RAM() 670 671 def get_cpu(): 672 673 "Return an instance representing the CPU." 674 675 return CPU() 676 677 # Test program providing coverage (necessary for compilers like Shedskin). 678 679 if __name__ == "__main__": 680 ula = get_ula() 681 ula.set_mode(2) 682 ula.reset() 683 ula.ram.fill(0x5800 - 320, 0x8000, encode((2, 7), 4)) 684 685 # Make a simple two-dimensional array of tuples (three-dimensional in pygame 686 # terminology). 687 688 a = update(ula) 689 690 # vim: tabstop=4 expandtab shiftwidth=4