1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
140 http://smithsonianchips.si.edu/augarten/p64.htm
141
142 A Note on 8-Bit Wide RAM Access
143 -------------------------------
144
145 It is worth considering the timing when 8 bits of data can be obtained at once
146 from the RAM chips:
147
148 Time (ns): 0-------------- 500------------- ...
149 2 MHz cycle: 0 1 ...
150 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
151 /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
152 ~RAS: /---\___________/---\___________ ...
153 ~CAS: /-------\_______/-------\_______ ...
154 Address events: A B A B ...
155 Data events: E E ...
156
157 ~RAS ops: 1 0 1 0 ...
158 ~CAS ops: 1 0 1 0 ...
159
160 Address ops: a b a b ...
161 Data ops: f s f ...
162
163 ~WE: ........W ...
164 PHI OUT: \_______/-------\_______/------- ...
165 CPU: L D L D ...
166 RnW: R R ...
167
168 Here, "E" indicates the availability of an entire byte.
169
170 Since only one fetch is required per 2MHz cycle, instead of two fetches for
171 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
172 be used to coordinate the necessary signalling.
173
174 Another conceivable simplification from using an 8-bit wide RAM access channel
175 with a single access within each 2MHz cycle is the possibility of allowing the
176 CPU to signal directly to the RAM instead of having the ULA perform the access
177 signalling on the CPU's behalf.
178
179 Note that 16MHz cycles would still be needed for the pixel clock in MODE 0,
180 which needs to output eight pixels per 2MHz cycle, producing 640 monochrome
181 pixels per 80-byte line.
182
183 CPU Clock Notes
184 ---------------
185
186 "The 6502 receives an external square-wave clock input signal on pin 37, which
187 is usually labeled PHI0. [...] This clock input is processed within the 6502
188 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
189 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
190 through two inverters and a push-pull amplifier. The same network of
191 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
192 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
193 available to external devices is so that they know when they can access the
194 CPU. When PHI1 is high, this means that external devices can read from the
195 address bus or data bus; when PHI2 is high, this means that external devices
196 can write to the data bus."
197
198 See: http://lateblt.livejournal.com/88105.html
199
200 "The 6502 has a synchronous memory bus where the master clock is divided into
201 two phases (Phase 1 and Phase 2). The address is always generated during Phase
202 1 and all memory accesses take place during Phase 2."
203
204 See: http://www.jmargolin.com/vgens/vgens.htm
205
206 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
207 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
208 when PHI1 is high.
209
210 Bandwidth Figures
211 -----------------
212
213 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
214 total lines, with 80 cycles occurring in the active periods of display
215 scanlines, the following bandwidth calculations can be performed:
216
217 Total theoretical maximum:
218 128 cycles * 312 lines
219 = 39936 bytes
220
221 MODE 0, 1, 2:
222 ULA: 80 cycles * 256 lines
223 = 20480 bytes
224 CPU: 48 cycles / 2 * 256 lines
225 + 128 cycles / 2 * (312 - 256) lines
226 = 9728 bytes
227
228 MODE 3:
229 ULA: 80 cycles * 24 rows * 8 lines
230 = 15360 bytes
231 CPU: 48 cycles / 2 * 24 rows * 8 lines
232 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
233 = 12288 bytes
234
235 MODE 4, 5:
236 ULA: 40 cycles * 256 lines
237 = 10240 bytes
238 CPU: (40 cycles + 48 cycles / 2) * 256 lines
239 + 128 cycles / 2 * (312 - 256) lines
240 = 19968 bytes
241
242 MODE 6:
243 ULA: 40 cycles * 24 rows * 8 lines
244 = 7680 bytes
245 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
246 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
247 = 19968 bytes
248
249 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
250 only uses every other access opportunity even in uncontended periods. See the
251 2MHz RAM Access enhancement below for bandwidth calculations that consider
252 this limitation removed.
253
254 A summary of the bandwidth figures is as follows (with extra timing details
255 described below):
256
257 Standard ULA % Total Slowdown BBC-10s BBC-34s
258 MODE 0, 1, 2 9728 bytes 24% 4.11 43s 105s
259 MODE 3 12288 bytes 31% 3.25 34s
260 MODE 4, 5 19968 bytes 50% 2 20s
261 MODE 6 19968 bytes 50% 2 20s 50s
262
263 The review of the Electron in Practical Computing (October 1983) provides a
264 concise overview of the RAM access limitations and gives timing comparisons
265 between modes and BBC Micro performance. In the above, "BBC-10s" is the
266 measured or stated time given for a program taking 10 seconds on the BBC
267 Micro, whereas "BBC-34s" is the apparently measured time given for the
268 "Persian" program taking 34 seconds to complete on the BBC Micro, with a
269 "quick" mode presumably switching to MODE 6 using the ULA directly in order to
270 reduce display bandwidth usage while the program draws to the screen.
271 Evidently, the measured slowdown is slightly lower than the theoretical
272 slowdown, most likely due to the running time not being entirely dominated by
273 RAM access performance characteristics.
274
275 Video Timing
276 ------------
277
278 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
279 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
280 (including the "colour burst"), and 1.65µs for the "front porch", totalling
281 12.05µs and thus leaving 51.95µs for the active video signal for each
282 scanline. As the Service Manual suggests in the oscilloscope traces, the
283 display information is transmitted more or less centred within the active
284 video period since the ULA will only be providing pixel data for 40µs in each
285 scanline.
286
287 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
288 each scanline can be divided into 1024 cycles, although only 640 at most are
289 actively used to provide pixel data. Pixel data production should only occur
290 within a certain period on each scanline, approximately 262 cycles after the
291 start of hsync:
292
293 active video period = 51.95µs
294 pixel data period = 40µs
295 total silent period = 51.95µs - 40µs = 11.95µs
296 silent periods (before and after) = 11.95µs / 2 = 5.975µs
297 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
298 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
299 pixel data period start cycle = 16.375µs / 62.5ns = 262
300
301 By choosing a number divisible by 8, the RAM access mechanism can be
302 synchronised with the pixel production. Thus, 256 is a more appropriate start
303 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
304 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
305 document) occurs at cycle 0.
306
307 To summarise:
308
309 HS signal starts at cycle 0 on each horizontal scanline
310 HS signal ends approximately 4µs later at cycle 64
311 Pixel data starts approximately 12µs later at cycle 256
312
313 "Re: Electron Memory Contention" provides measurements that appear consistent
314 with these calculations.
315
316 The "vertical blanking period", meaning the period before picture information
317 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
318 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
319 lines. Thus, the first visible scanline on the first field of a frame occurs
320 half way through the 23rd scanline period measured from the start of vsync
321 (indicated by "V" in the diagrams below):
322
323 10 20 23
324 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
325 Line from 1: 0 22 3
326 Line on screen: .:::::VVVVV::::: 12233445566
327 |_________________________________________________|
328 25 line vertical blanking period
329
330 In the second field of a frame, the first visible scanline coincides with the
331 24th scanline period measured from the start of line 313 in the frame:
332
333 310 336
334 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
335 Line from 313: 0 23 4
336 Line on screen: 88:::::VVVVV:::: 11223344
337 288 | |
338 |_________________________________________________|
339 25 line vertical blanking period
340
341 In order to consider only full lines, we might consider the start of each
342 frame to occur 23 lines after the start of vsync.
343
344 Again, it is likely that pixel data production should only occur on scanlines
345 within a certain period on each frame. The "625/50" document indicates that
346 only a certain region is "safe" to use, suggesting a vertically centred region
347 with approximately 15 blank lines above and below the picture. However, the
348 "PAL TV timing and voltages" document suggests 28 blank lines above and below
349 the picture. This would centre the 256 lines within the 312 lines of each
350 field and thus provide a start of picture approximately 5.5 or 5 lines after
351 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
352
353 To summarise:
354
355 CSYNC signal starts at cycle 0
356 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
357 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
358
359 See: http://en.wikipedia.org/wiki/PAL
360 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
361 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
362 http://lipas.uwasa.fi/~f76998/video/modes/
363 See: PAL TV timing and voltages
364 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
365 See: Line Standards
366 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
367 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
368 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
369 See: Re: Electron Memory Contention
370 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
371
372 RAM Integrated Circuits
373 -----------------------
374
375 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
376 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
377 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
378 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
379 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
380
381 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
382 the Samsung-produced KM41464 series is apparently equivalent to the Texas
383 Instruments 4164 chips presumably used in the Electron.
384
385 The TM4164EC4 series combines 4 64K x 1b units into a single package and
386 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
387 (in the Advanced User Guide but not the Service Manual), and it also has 22
388 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
389 of the individual 4164-15 modules, presumably allowing concurrent access to
390 the packaged memory units.
391
392 As far as currently available replacements are concerned, the NTE4164 is a
393 potential candidate: according to the Vetco Electronics entry, it is
394 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
395 parts include the NTE2164 and the NTE6664, both of which appear to have
396 largely the same performance and connection characteristics. Meanwhile, the
397 NTE21256 appears to be a 16-pin replacement with four times the capacity that
398 maintains the single data input and output pins. Using the NTE21256 as a
399 replacement for all ICs combined would be difficult because of the single bit
400 output.
401
402 Another device equivalent to the 4164-15 appears to be available under the
403 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
404 site lists data sheets for other devices on the same page, but these are
405 different and actually appear to be provided under the 41574 product code (but
406 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
407 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
408 employing 4 pins for both input and output.
409
410 Pins I/O pins Row access Column access
411 ---- -------- ---------- -------------
412 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
413 KM41464AP 18 4 150ns (15) 75ns (15)
414 NTE21256 16 1 + 1 150ns 75ns
415 HYB 4164-2 16 1 + 1 150ns 100ns
416 µPD41464 18 4 120ns (12) 60ns (12)
417
418 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
419 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
420 See: Dynamic RAMS
421 http://www.unicornelectronics.com/IC/DYNAMIC.html
422 See: New old stock 8x 4164 chips
423 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
424 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
425 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
426 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
427 http://www.vetco.net/catalog/product_info.php?products_id=2806
428 See: NTE4164 - IC-NMOS 64K DRAM 150NS
429 http://www.vetco.net/catalog/product_info.php?products_id=3680
430 See: NTE21256 - IC-256K DRAM 150NS
431 http://www.vetco.net/catalog/product_info.php?products_id=2799
432 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
433 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
434 See: NTE6664 - IC-MOS 64K DRAM 150NS
435 http://www.vetco.net/catalog/product_info.php?products_id=5213
436 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
437 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
438 See: 4164-150: MAJOR BRANDS
439 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
440 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
441 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
442 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
443 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
444 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
445 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
446 See: 41464-10: MAJOR BRANDS
447 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
448
449 Interrupts
450 ----------
451
452 The ULA generates IRQs (maskable interrupts) according to certain conditions
453 and these conditions are controlled by location &FE00:
454
455 * Vertical sync (bottom of displayed screen)
456 * 50MHz real time clock
457 * Transmit data empty
458 * Receive data full
459 * High tone detect
460
461 The ULA is also used to clear interrupt conditions through location &FE05. Of
462 particular significance is bit 7, which must be set if an NMI (non-maskable
463 interrupt) has occurred and has thus suspended ULA access to memory, restoring
464 the normal function of the ULA.
465
466 ROM Paging
467 ----------
468
469 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
470 mappings exist:
471
472 8 keyboard
473 9 keyboard (duplicate)
474 10 BASIC ROM
475 11 BASIC ROM (duplicate)
476
477 Paging in a ROM involves the following procedure:
478
479 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
480 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
481 selected.
482 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
483 whilst writing the desired ROM number n in bits 0 to 2.
484
485 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
486
487 Keyboard Access
488 ---------------
489
490 The keyboard pages appear to be accessed at 1MHz just like the RAM.
491
492 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
493
494 Shadow/Expanded Memory
495 ----------------------
496
497 The Electron exposes all sixteen address lines and all eight data lines
498 through the expansion bus. Using such lines, it is possible to provide
499 additional memory - typically sideways ROM and RAM - on expansion cards and
500 through cartridges, although the official cartridge specification provides
501 fewer address lines and only seeks to provide access to memory in 16K units.
502
503 Various modifications and upgrades were developed to offer "turbo"
504 capabilities to the Electron, permitting the CPU to access a separate 8K of
505 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
506 the ULA through additional logic. However, an enhanced ULA might support
507 independent CPU access to memory over the expansion bus by allowing itself to
508 be discharged from providing access to memory, potentially for a range of
509 addresses, and for the CPU to communicate with external memory uninterrupted.
510
511 Sideways RAM/ROM and Upper Memory Access
512 ----------------------------------------
513
514 Although the ULA controls the CPU clock, effectively slowing or stopping the
515 CPU when the ULA needs to access screen memory, it is apparently able to allow
516 the CPU to access addresses of &8000 and above - the upper region of memory -
517 at 2MHz independently of any access to RAM that the ULA might be performing,
518 only blocking the CPU if it attempts to access addresses of &7FFF and below
519 during any ULA memory access - the lower region of memory - by stopping or
520 stalling its clock.
521
522 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
523 CPU clock if the line goes low, when the CPU is attempting to access the lower
524 region of memory.
525
526 Hardware Scrolling (and Enhancement)
527 ------------------------------------
528
529 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
530 the least significant 5 bits being zero, thus limiting the scrolling
531 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
532 using the same layout of these addresses.
533
534 |--&FE02--------------| |--&FE03--------------|
535 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
536
537 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
538
539 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
540 memory to pixel locations is character oriented. A change in 8 bytes would
541 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
542 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
543 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
544 Guide).
545
546 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
547 of changing the screen address by 2 bytes is the change in the number of lines
548 from the initial and final character rows that need reading by the ULA, which
549 would need to maintain this state information (although this is a relatively
550 trivial change). Another pitfall is the complication that might be introduced
551 to software writing bitmaps of character height to the screen.
552
553 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
554
555 Enhancement: Mode Layouts
556 -------------------------
557
558 Merely changing the screen memory mappings in order to have Archimedes-style
559 row-oriented screen addresses (instead of character-oriented addresses) could
560 be done for the existing modes, but this might not be sufficiently beneficial,
561 especially since accessing regions of the screen would involve incrementing
562 pointers by amounts that are inconvenient on an 8-bit CPU.
563
564 However, instead of using a Archimedes-style mapping, column-oriented screen
565 addresses could be more feasibly employed: incrementing the address would
566 reference the vertical screen location below the currently-referenced location
567 (just as occurs within characters using the existing ULA); instead of
568 returning to the top of the character row and referencing the next horizontal
569 location after eight bytes, the address would reference the next character row
570 and continue to reference locations downwards over the height of the screen
571 until reaching the bottom; at the bottom, the next location would be the next
572 horizontal location at the top of the screen.
573
574 In other words, the memory layout for the screen would resemble the following
575 (for MODE 2):
576
577 &3000 &3100 ... &7F00
578 &3001 &3101
579 ... ...
580 &3007
581 &3008
582 ...
583 ... ...
584 &30FF ... &7FFF
585
586 Since there are 256 pixel rows, each column of locations would be addressable
587 using the low byte of the address. Meanwhile, the high byte would be
588 incremented to address different columns. Thus, addressing screen locations
589 would become a lot more convenient and potentially much more efficient for
590 certain kinds of graphical output.
591
592 One potential complication with this simplified addressing scheme arises with
593 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
594 with the existing ULA) would be achieved by incrementing or decrementing the
595 screen start address; by one character row, it would involve adding or
596 subtracting 8. However, the ULA only supports multiples of 64 when changing the
597 screen start address. Thus, if such a scheme were to be adopted, three
598 additional bits would need to be supported in the screen start register (see
599 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
600 scrolling would be much improved even under the severe constraints of the
601 existing ULA: only adjustments of 256 to the screen start address would be
602 required to produce single-location scrolling of as few as two pixels in MODE 2
603 (four pixels in MODEs 1 and 5, eight pixels otherwise).
604
605 More disruptive is the effect of this alternative layout on software.
606 Presumably, compatibility with the BBC Micro was the primary goal of the
607 Electron's hardware design. With the character-oriented screen layout in
608 place, system software (and application software accessing the screen
609 directly) would be relying on this layout to run on the Electron with little
610 or no modification. Although it might have been possible to change the system
611 software to use this column-oriented layout instead, this would have incurred
612 a development cost and caused additional work porting things like games to the
613 Electron. Moreover, a separate branch of the software from that supporting the
614 BBC Micro and closer derivatives would then have needed maintaining.
615
616 The decision to use the character-oriented layout in the BBC Micro may have
617 been related to the choice of circuitry and to facilitate a convenient
618 hardware implementation, and by the time the Electron was planned, it was too
619 late to do anything about this somewhat unfortunate choice.
620
621 Pixel Layouts
622 -------------
623
624 The pixel layouts are as follows:
625
626 Modes Depth (bpp) Pixels (from bits)
627 ----- ----------- ------------------
628 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
629 1, 5 2 73 62 51 40
630 2 4 7531 6420
631
632 Since the ULA reads a half-byte at a time, one might expect it to attempt to
633 produce pixels for every half-byte, as opposed to handling entire bytes.
634 However, the pixel layout is not conducive to producing pixels as soon as a
635 half-byte has been read for a given full-byte location: in 1bpp modes the
636 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
637 data is spread across the entire byte in different ways.
638
639 An alternative arrangement might be as follows:
640
641 Modes Depth (bpp) Pixels (from bits)
642 ----- ----------- ------------------
643 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
644 1, 5 2 76 54 32 10
645 2 4 7654 3210
646
647 Just as the mode layouts were presumably decided by compatibility with the BBC
648 Micro, the pixel layouts will have been maintained for similar reasons.
649 Unfortunately, this layout prevents any optimisation of the ULA for handling
650 half-byte pixel data generally.
651
652 Enhancement: The Missing MODE 4
653 -------------------------------
654
655 The Electron inherits its screen mode selection from the BBC Micro, where MODE
656 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
657 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
658 however, and they are merely implemented by skipping two scanlines in every
659 ten after the eight required to produce a character line. Thus, such modes
660 provide a 24-row display.
661
662 In principle, nothing prevents this "text mode" effect being applied to other
663 modes. The 20-column modes are not well-suited to displaying text, which
664 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
665 2. Although the need for a non-monochrome 40-column text mode is addressed by
666 MODE 7 on the BBC Micro, the Electron lacks such a mode.
667
668 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
669 would occupy MODE 4 instead of the current MODE 4:
670
671 Screen mode Size (kilobytes) Colours Rows Resolution
672 ----------- ---------------- ------- ---- ----------
673 0 20 2 32 640x256
674 1 20 4 32 320x256
675 2 20 16 32 160x256
676 3 16 2 24 640x256
677 4 (new) 16 4 24 320x256
678 4 (old) 10 2 32 320x256
679 5 10 4 32 160x256
680 6 8 2 24 320x256
681
682 Thus, for increasing mode numbers, the size of each mode would be the same or
683 less than the preceding mode.
684
685 Enhancement: 2MHz RAM Access
686 ----------------------------
687
688 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
689 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
690 if the ULA still needed to access the RAM), one useful enhancement would be a
691 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
692 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
693 3.
694
695 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
696
697 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
698 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
699
700 In MODE 4 to 6:
701
702 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
703 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
704
705 This would improve CPU bandwidth as follows:
706
707 Standard ULA Enhanced ULA % Total Bandwidth Speedup
708 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
709 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
710 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
711 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
712
713 (Here, the uncontended total 2MHz bandwidth for a display period would be
714 39936 bytes, being 128 cycles per line over 312 lines.)
715
716 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
717 because all access opportunities to RAM are doubled. Meanwhile, in the other
718 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
719 doubled, but the CPU bandwidth increase is still significant.
720
721 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
722 within the time constraints of 2MHz operation. There is no time remaining in a
723 2MHz cycle for the CPU to receive and process any retrieved data once the
724 necessary signalling has been performed. The only way for the CPU to be able
725 to access the RAM quickly enough would be to do away with the double 4-bit
726 access mechanism and to have a single 8-bit channel to the memory. This would
727 require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
728 would also potentially simplify the ULA.
729
730 Enhancement: Region Blanking
731 ----------------------------
732
733 The problem of permitting character-oriented blitting in programs whilst
734 scrolling the screen by sub-character amounts could be mitigated by permitting
735 a region of the display to be blank, such as the final lines of the display.
736 Consider the following vertical scrolling by 2 bytes that would cause an
737 initial character row of 6 lines and a final character row of 2 lines:
738
739 6 lines - initial, partial character row
740 248 lines - 31 complete rows
741 2 lines - final, partial character row
742
743 If a routine were in use that wrote 8 line bitmaps to the partial character
744 row now split in two, it would be advisable to hide one of the regions in
745 order to prevent content appearing in the wrong place on screen (such as
746 content meant to appear at the top "leaking" onto the bottom). Blanking 6
747 lines would be sufficient, as can be seen from the following cases.
748
749 Scrolling up by 2 lines:
750
751 6 lines - initial, partial character row
752 240 lines - 30 complete rows
753 4 lines - part of 1 complete row
754 -----------------------------------------------------------------
755 4 lines - part of 1 complete row (hidden to maintain 250 lines)
756 2 lines - final, partial character row (hidden)
757
758 Scrolling down by 2 lines:
759
760 2 lines - initial, partial character row
761 248 lines - 31 complete rows
762 ----------------------------------------------------------
763 6 lines - final, partial character row (hidden)
764
765 Thus, in this case, region blanking would impose a 250 line display with the
766 bottom 6 lines blank.
767
768 See the description of the display suspend enhancement for a more efficient
769 way of blanking lines than merely blanking the palette whilst allowing the CPU
770 to perform useful work during the blanking period.
771
772 To control the blanking or suspending of lines at the top and bottom of the
773 display, a memory location could be dedicated to the task: the upper 4 bits
774 could define a blanking region of up to 16 lines at the top of the screen,
775 whereas the lower 4 bits could define such a region at the bottom of the
776 screen. If more lines were required, two locations could be employed, allowing
777 the top and bottom regions to occupy the entire screen.
778
779 Enhancement: Screen Height Adjustment
780 -------------------------------------
781
782 The height of the screen could be configurable in order to reduce screen
783 memory consumption. This is not quite done in MODE 3 and 6 since the start of
784 the screen appears to be rounded down to the nearest page, but by reducing the
785 height by amounts more than a page, savings would be possible. For example:
786
787 Screen width Depth Height Bytes per line Saving in bytes Start address
788 ------------ ----- ------ -------------- --------------- -------------
789 640 1 252 80 320 &3140 -> &3100
790 640 1 248 80 640 &3280 -> &3200
791 320 1 240 40 640 &5A80 -> &5A00
792 320 2 240 80 1280 &3500
793
794 Screen Mode Selection
795 ---------------------
796
797 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
798 range of modes, the other bits of &FE*7 (related to sound, cassette
799 input/output and the Caps Lock LED) would need to be reassigned and bit 0
800 potentially being made available for use.
801
802 Enhancement: Palette Definition
803 -------------------------------
804
805 Since all memory accesses go via the ULA, an enhanced ULA could employ more
806 specific addresses than &FE*X to perform enhanced functions. For example, the
807 palette control is done using &FE*8-F and merely involves selecting predefined
808 colours, whereas an enhanced ULA could support the redefinition of all 16
809 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
810 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
811 specifications similar to those used on the Archimedes.
812
813 The principal limitation here is actually the hardware: the Electron has only
814 a single output line for each of the red, green and blue channels, and if
815 those outputs are strictly digital and can only be set to a "high" and "low"
816 value, then only the existing eight colours are possible. If a modern ULA were
817 able to output analogue values (or values at well-defined points between the
818 high and low values, such as the half-on value supported by the Amstrad CPC
819 series), it would still need to be assessed whether the circuitry could
820 successfully handle and propagate such values. Various sources indicate that
821 only "TTL levels" are supported by the RGB output circuit, and since there are
822 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
823 is likely that the ULA is expected to provide only "high" or "low" values.
824
825 Short of adding extra outputs from the ULA (either additional red, green and
826 blue outputs or a combined intensity output), another approach might involve
827 some kind of modulation where an output value might be encoded in multiple
828 pulses at a higher frequency than the pixel frequency. However, this would
829 demand additional circuitry outside the ULA, and component RGB monitors would
830 probably not be able to take advantage of this feature; only UHF and composite
831 video devices (the latter with the composite video colour support enabled on
832 the Electron's circuit board) would potentially benefit.
833
834 Flashing Colours
835 ----------------
836
837 According to the Advanced User Guide, "The cursor and flashing colours are
838 entirely generated in software: This means that all of the logical to physical
839 colour map must be changed to cause colours to flash." This appears to suggest
840 that the palette registers must be updated upon the flash counter - read and
841 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
842 colour pairs to be any combination of colours might be possible, instead of
843 having colour complements as pairs.
844
845 It is conceivable that the interrupt code responsible does the simple thing
846 and merely inverts the current values for any logical colours (LC) for which
847 the associated physical colour (as supplied as the second parameter to the VDU
848 19 call) has the top bit of its four bit value set. These top bits are not
849 recorded in the palette registers but are presumably recorded separately and
850 used to build bitmaps as follows:
851
852 LC 2 colour 4 colour 16 colour 4-bit value for inversion
853 -- -------- -------- --------- -------------------------
854 0 00010001 00010001 00010001 1, 1, 1
855 1 01000100 00100010 00010001 4, 2, 1
856 2 01000100 00100010 4, 2
857 3 10001000 00100010 8, 2
858 4 00010001 1
859 5 00010001 1
860 6 00100010 2
861 7 00100010 2
862 8 01000100 4
863 9 01000100 4
864 10 10001000 8
865 11 10001000 8
866 12 01000100 4
867 13 01000100 4
868 14 10001000 8
869 15 10001000 8
870
871 Inversion value calculation:
872
873 2 colour formula: 1 << (colour * 2)
874 4 colour formula: 1 << colour
875 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
876
877 For example, where logical colour 0 has been mapped to a physical colour in
878 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
879 the inversion operation. (The lower three bits of the physical colour would be
880 used to set the underlying colour information affected by the inversion
881 operation.)
882
883 An operation in the interrupt code would then combine the bitmaps for all
884 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
885 combined for groups of logical colours as follows:
886
887 Logical colours
888 ---------------
889 0, 2, 8, 10
890 4, 6, 12, 14
891 5, 7, 13, 15
892 1, 3, 9, 11
893
894 These combined bitmaps would be EORed with the existing palette register
895 values in order to perform the value inversion necessary to produce the
896 flashing effect.
897
898 Thus, in the VDU 19 operation, the appropriate inversion value would be
899 calculated for the logical colour, and this value would then be combined with
900 other inversion values in a dedicated memory location corresponding to the
901 colour's group as indicated above. Meanwhile, the palette channel values would
902 be derived from the lower three bits of the specified physical colour and
903 combined with other palette data in dedicated memory locations corresponding
904 to the palette registers.
905
906 Interestingly, although flashing colours on the BBC Micro are controlled by
907 toggling bit 0 of the &FE20 control register location for the Video ULA, the
908 actual colour inversion is done in hardware.
909
910 Enhancement: Palette Definition Lists
911 -------------------------------------
912
913 It can be useful to redefine the palette in order to change the colours
914 available for a particular region of the screen, particularly in modes where
915 the choice of colours is constrained, and if an increased colour depth were
916 available, palette redefinition would be useful to give the illusion of more
917 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
918 by using interrupt-driven timers, but a more efficient approach would involve
919 presenting lists of palette definitions to the ULA so that it can change the
920 palette at a particular display line.
921
922 One might define a palette redefinition list in a region of memory and then
923 communicate its contents to the ULA by writing the address and length of the
924 list, along with the display line at which the palette is to be changed, to
925 ULA registers such that the ULA buffers the list and performs the redefinition
926 at the appropriate time. Throughput/bandwidth considerations might impose
927 restrictions on the practical length of such a list, however.
928
929 Enhancement: Display Synchronisation Interrupts
930 -----------------------------------------------
931
932 When completing each scanline of the display, the ULA could trigger an
933 interrupt. Since this might impact system performance substantially, the
934 feature would probably need to be configurable, and it might be sufficient to
935 have an interrupt only after a certain number of display lines instead.
936 Permitting the CPU to take action after eight lines would allow palette
937 switching and other effects to occur on a character row basis.
938
939 The ULA provides an interrupt at the end of the display period, presumably so
940 that software can schedule updates to the screen, avoid flickering or tearing,
941 and so on. However, some applications might benefit from an interrupt at, or
942 just before, the start of the display period so that palette modifications or
943 similar effects could be scheduled.
944
945 Enhancement: Palette-Free Modes
946 -------------------------------
947
948 Palette-free modes might be defined where bit values directly correspond to
949 the red, green and blue channels, although this would mostly make sense only
950 for modes with depths greater than the standard 4 bits per pixel, and such
951 modes would require more memory than MODE 2 if they were to have an acceptable
952 resolution.
953
954 Enhancement: Display Suspend
955 ----------------------------
956
957 Especially when writing to the screen memory, it could be beneficial to be
958 able to suspend the ULA's access to the memory, instead producing blank values
959 for all screen pixels until a program is ready to reveal the screen. This is
960 different from palette blanking since with a blank palette, the ULA is still
961 reading screen memory and translating its contents into pixel values that end
962 up being blank.
963
964 This function is reminiscent of a capability of the ZX81, albeit necessary on
965 that hardware to reduce the load on the system CPU which was responsible for
966 producing the video output. By allowing display suspend on the Electron, the
967 performance benefit would be derived from giving the CPU full access to the
968 memory bandwidth.
969
970 The region blanking feature mentioned above could be implemented using this
971 enhancement instead of employing palette blanking for the affected lines of
972 the display.
973
974 Enhancement: Memory Filling
975 ---------------------------
976
977 A capability that could be given to an enhanced ULA is that of permitting the
978 ULA to write to screen memory as well being able to read from it. Although
979 such a capability would probably not be useful in conjunction with the
980 existing read operations when producing a screen display, and insufficient
981 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
982 capability could be offered during a display suspend period (as described
983 above), permitting a more efficient mechanism to rapidly fill memory with a
984 predetermined value.
985
986 This capability could also support block filling, where the limits of the
987 filled memory would be defined by the position and size of a screen area,
988 although this would demand the provision of additional registers in the ULA to
989 retain the details of such areas and additional logic to control the fill
990 operation.
991
992 Enhancement: Region Filling
993 ---------------------------
994
995 An alternative to memory writing might involve indicating regions using
996 additional registers or memory where the ULA fills regions of the screen with
997 content instead of reading from memory. Unlike hardware sprites which should
998 realistically provide varied content, region filling could employ single
999 colours or patterns, and one advantage of doing so would be that the ULA need
1000 not access memory at all within a particular region.
1001
1002 Regions would be defined on a row-by-row basis. Instead of reading memory and
1003 blitting a direct representation to the screen, the ULA would read region
1004 definitions containing a start column, region width and colour details. There
1005 might be a certain number of definitions allowed per row, or the ULA might
1006 just traverse an ordered list of such definitions with each one indicating the
1007 row, start column, region width and colour details.
1008
1009 One could even compress this information further by requiring only the row,
1010 start column and colour details with each subsequent definition terminating
1011 the effect of the previous one. However, one would also need to consider the
1012 convenience of preparing such definitions and whether efficient access to
1013 definitions for a particular row might be desirable. It might also be
1014 desirable to avoid having to prepare definitions for "empty" areas of the
1015 screen, effectively making the definition of the screen contents employ
1016 run-length encoding and employ only colour plus length information.
1017
1018 One application of region filling is that of simple 2D and 3D shape rendering.
1019 Although it is entirely possible to plot such shapes to the screen and have
1020 the ULA blit the memory contents to the screen, such operations consume
1021 bandwidth both in the initial plotting and in the final transfer to the
1022 screen. Region filling would reduce such bandwidth usage substantially.
1023
1024 This way of representing screen images would make certain kinds of images
1025 unfeasible to represent - consider alternating single pixel values which could
1026 easily occur in some character bitmaps - even if an internal queue of regions
1027 were to be supported such that the ULA could read ahead and buffer such
1028 "bandwidth intensive" areas. Thus, the ULA might be better served providing
1029 this feature for certain areas of the display only as some kind of special
1030 graphics window.
1031
1032 Enhancement: Hardware Sprites
1033 -----------------------------
1034
1035 An enhanced ULA might provide hardware sprites, but this would be done in an
1036 way that is incompatible with the standard ULA, since no &FE*X locations are
1037 available for allocation. To keep the facility simple, hardware sprites would
1038 have a standard byte width and height.
1039
1040 The specification of sprites could involve the reservation of 16 locations
1041 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
1042 location pair referring to the sprite data. By limiting the ULA to dealing
1043 with a fixed number of sprites, the work required inside the ULA would be
1044 reduced since it would avoid having to deal with arbitrary numbers of sprites.
1045
1046 The principal limitation on providing hardware sprites is that of having to
1047 obtain sprite data, given that the ULA is usually required to retrieve screen
1048 data, and given the lack of memory bandwidth available to retrieve sprite data
1049 (particularly from multiple sprites supposedly at the same position) and
1050 screen data simultaneously. Although the ULA could potentially read sprite
1051 data and screen data in alternate memory accesses in screen modes where the
1052 bandwidth is not already fully utilised, this would result in a degradation of
1053 performance.
1054
1055 Enhancement: Additional Screen Mode Configurations
1056 --------------------------------------------------
1057
1058 Alternative screen mode configurations could be supported. The ULA has to
1059 produce 640 pixel values across the screen, with pixel doubling or quadrupling
1060 employed to fill the screen width:
1061
1062 Screen width Columns Scaling Depth Bytes
1063 ------------ ------- ------- ----- -----
1064 640 80 x1 1 80
1065 320 40 x2 1, 2 40, 80
1066 160 20 x4 2, 4 40, 80
1067
1068 It must also use at most 80 byte-sized memory accesses to provide the
1069 information for the display. Given that characters must occupy an 8x8 pixel
1070 array, if a configuration featuring anything other than 20, 40 or 80 character
1071 columns is to be supported, compromises must be made such as the introduction
1072 of blank pixels either between characters (such as occurs between rows in MODE
1073 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1074 in MODE 3 and 6). Consider the following configuration:
1075
1076 Screen width Columns Scaling Depth Bytes Blank
1077 ------------ ------- ------- ----- ------ -----
1078 208 26 x3 1, 2 26, 52 16
1079
1080 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1081 colours could be provided, with 16 blank pixel values (out of a total of 640)
1082 generated either at the start or end (or split between the start and end) of
1083 each scanline.
1084
1085 Enhancement: Character Attributes
1086 ---------------------------------
1087
1088 The BBC Micro MODE 7 employs something resembling character attributes to
1089 support teletext displays, but depends on circuitry providing a character
1090 generator. The ZX Spectrum, on the other hand, provides character attributes
1091 as a means of colouring bitmapped graphics. Although such a feature is very
1092 limiting as the sole means of providing multicolour graphics, in situations
1093 where the choice is between low resolution multicolour graphics or high
1094 resolution monochrome graphics, character attributes provide a potentially
1095 useful compromise.
1096
1097 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1098 640) to the video output, doing so by either emptying its pixel buffer on a
1099 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1100 than one cycle. For example for a screen mode having 640 pixels in width:
1101
1102 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1103 Reads: B B
1104 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1105
1106 And for a screen mode having 320 pixels in width:
1107
1108 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1109 Reads: B
1110 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1111
1112 However, in modes where less than 80 bytes are required to generate the pixel
1113 values, an enhanced ULA might be able to read additional bytes between those
1114 providing the bitmapped graphics data:
1115
1116 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1117 Reads: B A
1118 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1119
1120 These additional bytes could provide colour information for the bitmapped data
1121 in the following character column (of 8 pixels). Since it would be desirable
1122 to apply attribute data to the first column, the initial 8 cycles might be
1123 configured to not produce pixel values.
1124
1125 For an entire character, attribute data need only be read for the first row of
1126 pixels for a character. The subsequent rows would have attribute information
1127 applied to them, although this would require the attribute data to be stored
1128 in some kind of buffer. Thus, the following access pattern would be observed:
1129
1130 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1131
1132 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1133 data:
1134
1135 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1136 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1137 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1138 ...
1139
1140 See below for a discussion of using this for character data as well.
1141
1142 A whole byte used for colour information for a whole character would result in
1143 a choice of 256 colours, and this might be somewhat excessive. By only reading
1144 attribute bytes at every other opportunity, a choice of 16 colours could be
1145 applied individually to two characters.
1146
1147 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1148 Reads: B A B -
1149 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1150
1151 Further reductions in attribute data access, offering 4 colours for every
1152 character in a four character block, for example, might also be worth
1153 considering.
1154
1155 Consider the following configurations for screen modes with a colour depth of
1156 1 bit per pixel for bitmap information:
1157
1158 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1159 ------------ ------- ------- --------- --------- ------- ------------
1160 320 40 x2 40 40 256 &5300
1161 320 40 x2 40 20 16 &5580 -> &5500
1162 320 40 x2 40 10 4 &56C0 -> &5600
1163 208 26 x3 26 26 256 &62C0 -> &6200
1164 208 26 x3 26 13 16 &6460 -> &6400
1165
1166 Enhancement: Text-Only Modes using Character and Attribute Data
1167 ---------------------------------------------------------------
1168
1169 In modes 3 and 6, the blank display lines could be used to retrieve character
1170 and attribute data instead of trying to insert it between bitmap data accesses,
1171 but this data would then need to be retained:
1172
1173 Reads: A C A C A C A C A C A C A C A C ...
1174 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1175
1176 Only attribute (A) and character (C) reads would require screen memory
1177 storage. Bitmap data reads (B) would involve either accesses to memory to
1178 obtain character definition details or could, at the cost of special storage
1179 in the ULA, involve accesses within the ULA that would then free up the RAM.
1180 However, the CPU would not benefit from having any extra access slots due to
1181 the limitations of the RAM access mechanism.
1182
1183 A scheme without caching might be possible. The same line of memory addresses
1184 might be visited over and over again for eight display lines, with an index
1185 into the bitmap data being incremented from zero to seven. The access patterns
1186 would look like this:
1187
1188 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1189 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1190 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1191 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1192 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1193 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1194 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1195 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1196
1197 The bandwidth requirements would be the sum of the accesses to read the
1198 character values (repeatedly) and those to read the bitmap data to reproduce
1199 the characters on screen.
1200
1201 Enhancement: MODE 7 Emulation using Character Attributes
1202 --------------------------------------------------------
1203
1204 If the scheme of applying attributes to character regions were employed to
1205 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1206 following configuration would be required:
1207
1208 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1209 ------------ ------- ---- --------- --------- ------- ------------
1210 320 40 25 40 20 16 &5ECC -> &5E00
1211 320 40 25 40 10 4 &5FC6 -> &5F00
1212
1213 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1214 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1215 at least make a limited 40-column multicolour mode available as a substitute
1216 for MODE 7.
1217
1218 Using the text-only enhancement with caching of data or with repeated reads of
1219 the same character data line for eight display lines, the storage requirements
1220 would be diminished substantially:
1221
1222 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1223 ------------ ------- ---- --------- --------- ------- ------------
1224 320 40 25 40 20 16 &7A94 -> &7A00
1225 320 40 25 40 10 4 &7B1E -> &7B00
1226 320 40 25 40 5 2 &7B9B -> &7B00
1227 320 40 25 40 0 (2) &7C18 -> &7C00
1228 640 80 25 80 40 16 &7448 -> &7400
1229 640 80 25 80 20 4 &763C -> &7600
1230 640 80 25 80 10 2 &7736 -> &7700
1231 640 80 25 80 0 (2) &7830 -> &7800
1232
1233 Note that the colours describe the locally defined attributes for each
1234 character. When no attribute information is provided, the colours are defined
1235 globally.
1236
1237 Enhancement: Compressed Character Data
1238 --------------------------------------
1239
1240 Another observation about text-only modes is that they only need to store a
1241 restricted set of bitmapped data values. Encoding this set of values in a
1242 smaller unit of storage than a byte could possibly help to reduce the amount
1243 of storage and bandwidth required to reproduce the characters on the display.
1244
1245 Enhancement: High Resolution Graphics
1246 -------------------------------------
1247
1248 Screen modes with higher resolutions and larger colour depths might be
1249 possible, but this would in most cases involve the allocation of more screen
1250 memory, and the ULA would probably then be obliged to page in such memory for
1251 the CPU to be able to sensibly access it all.
1252
1253 Enhancement: Genlock Support
1254 ----------------------------
1255
1256 The ULA generates a video signal in conjunction with circuitry producing the
1257 output features necessary for the correct display of the screen image.
1258 However, it appears that the ULA drives the video synchronisation mechanism
1259 instead of reacting to an existing signal. Genlock support might be possible
1260 if the ULA were made to be responsive to such external signals, resetting its
1261 address generators upon receiving synchronisation events.
1262
1263 Enhancement: Improved Sound
1264 ---------------------------
1265
1266 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1267 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1268 cassette I/O), thus making it impossible to support multiple channels within
1269 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1270 and an enhanced ULA could adopt this interface.
1271
1272 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1273 functionality of this chip could be emulated for enhanced sound, with a subset
1274 of the functionality exposed via the &FE*6 interface.
1275
1276 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1277 See: http://www.smspower.org/Development/SN76489
1278
1279 Enhancement: Waveform Upload
1280 ----------------------------
1281
1282 As with a hardware sprite function, waveforms could be uploaded or referenced
1283 using locations as registers referencing memory regions.
1284
1285 Enhancement: Sound Input/Output
1286 -------------------------------
1287
1288 Since the ULA already controls audio input/output for cassette-based data, it
1289 would have been interesting to entertain the idea of sampling and output of
1290 sounds through the cassette interface. However, a significant amount of
1291 circuitry is employed to process the input signal for use by the ULA and to
1292 process the output signal for recording.
1293
1294 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1295
1296 Enhancement: BBC ULA Compatibility
1297 ----------------------------------
1298
1299 Although some new ULA functions could be defined in a way that is also
1300 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1301 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1302 map, but controls various functions specific to the 6845 video controller;
1303 &FE08-F is reserved for the serial controller. It therefore becomes possible
1304 to disregard compatibility where compatibility is already disregarded for a
1305 particular area of functionality.
1306
1307 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1308 control over the palette (using address &FE21, compared to &FE07-F on the
1309 Electron) and other system-specific functions. Since the location usage is
1310 generally incompatible, this region could be reused for other purposes.
1311
1312 Enhancement: Increased RAM, ULA and CPU Performance
1313 ---------------------------------------------------
1314
1315 More modern implementations of the hardware might feature faster RAM coupled
1316 with an increased ULA clock frequency in order to increase the bandwidth
1317 available to the ULA and to the CPU in situations where the ULA is not needed
1318 to perform work. A ULA employing a 32MHz clock would be able to complete the
1319 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1320 to access the RAM for the following 250ns even in display modes requiring the
1321 retrieval of a byte for the display every 500ns. The CPU could, subject to
1322 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1323
1324 A scheme such as that described above would have a similar effect to the
1325 scheme employed in the BBC Micro, although the latter made use of RAM with a
1326 wider bandwidth in order to complete memory transfers within 250ns and thus
1327 permit the CPU to run continuously at 2MHz.
1328
1329 Higher bandwidth could potentially be used to implement exotic features such
1330 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1331 concurrent with the production of the display image.
1332
1333 Enhancement: Multiple CPU Stacks and Zero Pages
1334 -----------------------------------------------
1335
1336 The 6502 maintains a stack for subroutine calls and register storage in page
1337 &01. Although the stack register can be manipulated using the TSX and TXS
1338 instructions, thereby permitting the maintenance of multiple stack regions and
1339 thus the potential coexistence of multiple programs each using a separate
1340 region, only programs that make little use of the stack (perhaps avoiding
1341 deeply-nested subroutine invocations and significant register storage) would
1342 be able to coexist without overwriting each other's stacks.
1343
1344 One way that this issue could be alleviated would involve the provision of a
1345 facility to redirect accesses to page &01 to other areas of memory. The ULA
1346 would provide a register that defines a physical page for the use of the CPU's
1347 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1348 change the asserted address lines to redirect the access to the appropriate
1349 physical region.
1350
1351 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1352 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1353 register value before the access is made. Where multiple programs coexist,
1354 upon switching programs, the register would be updated to point the ULA to the
1355 appropriate stack location, thus providing a simple memory management unit
1356 (MMU) capability.
1357
1358 In a similar fashion, zero page accesses could also be redirected so that code
1359 could run from sideways RAM and have zero page operations redirected to "upper
1360 memory" - for example, to page &BE (with stack accesses redirected to page
1361 &BF, perhaps) - thereby permitting most CPU operations to occur without
1362 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1363 CPU as it contends with the ULA for memory access.
1364
1365 Such facilities could also be provided by a separate circuit between the CPU
1366 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1367 such boards, no additional RAM would be provided: all memory accesses would
1368 occur as normal through the ULA, albeit redirected when configured
1369 appropriately.
1370
1371 ULA Pin Functions
1372 -----------------
1373
1374 The functions of the ULA pins are described in the Electron Service Manual. Of
1375 interest to video processing are the following:
1376
1377 CSYNC (low during horizontal or vertical synchronisation periods, high
1378 otherwise)
1379
1380 HS (low during horizontal synchronisation periods, high otherwise)
1381
1382 RED, GREEN, BLUE (pixel colour outputs)
1383
1384 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1385
1386 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1387
1388 More general memory access pins:
1389
1390 RAM0...RAM3 (data lines to/from the RAM)
1391
1392 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1393
1394 RAS (row address strobe setting the row address on a negative edge - see the
1395 timing notes)
1396
1397 CAS (column address strobe setting the column address on a negative edge -
1398 see the timing notes)
1399
1400 WE (sets write enable with logic 0, read with logic 1)
1401
1402 ROM (select data access from ROM)
1403
1404 CPU-oriented memory access pins:
1405
1406 A0...A15 (CPU address lines)
1407
1408 PD0...PD7 (CPU data lines)
1409
1410 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1411
1412 Interrupt-related pins:
1413
1414 NMI (CPU request for uninterrupted 1MHz access to memory)
1415
1416 IRQ (signal event to CPU)
1417
1418 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1419 CPU's RST pin)
1420
1421 RST (master reset for the CPU signalled on power-up and by the Break key)
1422
1423 Keyboard-related pins:
1424
1425 KBD0...KBD3 (keyboard inputs)
1426
1427 CAPS LOCK (control status LED)
1428
1429 Sound-related pins:
1430
1431 SOUND O/P (sound output using internal oscillator)
1432
1433 Cassette-related pins:
1434
1435 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1436
1437 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1438
1439 CAS RC (detect high tone)
1440
1441 CAS MO (motor relay output)
1442
1443 ÷13 IN (~1200 baud clock input)
1444
1445 ULA Socket
1446 ----------
1447
1448 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1449
1450 References
1451 ----------
1452
1453 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1454
1455 About this Document
1456 -------------------
1457
1458 The most recent version of this document and accompanying distribution should
1459 be available from the following location:
1460
1461 http://hgweb.boddie.org.uk/ULA
1462
1463 Copyright and licence information can be found in the docs directory of this
1464 distribution - see docs/COPYING.txt for more information.