1 Principal Design and Feature Constraints
2 ----------------------------------------
3
4 The features of the ULA are limited by the amount of time and resources that
5 can be allocated to each activity necessary to support such features given the
6 fundamental obligations of the unit. Maintaining a screen display based on the
7 contents of RAM itself requires the ULA to have exclusive access to such
8 hardware resources for a significant period of time. Whilst other elements of
9 the ULA can in principle run in parallel with this activity, they cannot also
10 access the RAM. Consequently, other features that might use the RAM must
11 accept a reduced allocation of that resource in comparison to a hypothetical
12 architecture where concurrent RAM access is possible.
13
14 Thus, the principal constraint for many features is bandwidth. The duration of
15 access to hardware resources is one aspect of this; the rate at which such
16 resources can be accessed is another. For example, the RAM is not fast enough
17 to support access more frequently than one byte per 2MHz cycle, and for screen
18 modes involving 80 bytes of screen data per scanline, there are no free cycles
19 for anything other than the production of pixel output during the active
20 scanline periods.
21
22 Timing
23 ------
24
25 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
26 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
27 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
28 312 ~= 128 cycles). This is consistent with the observation that each scanline
29 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
30 out of 64 microseconds in each scanline.
31
32 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
33 each providing two bits of each byte) using two cycles within the 500ns period
34 of the 2MHz clock to complete each access operation. Since the CPU and ULA
35 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
36 effectively run at 1MHz (since every other 500ns period involves the ULA
37 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
38 frequency is divided by the ULA (IC1) depending on the screen mode in use.
39
40 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
41 patterns corresponding to 16MHz cycles are required:
42
43 Time (ns): 0-------------- 500------------ ...
44 2 MHz cycle: 0 1 ...
45 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
46 ~RAS: 0 1 0 1 ...
47 ~CAS: 0 1 0 1 0 1 0 1 ...
48 A B C A B C ...
49 F S F S ...
50 a b c a b c ...
51
52 Here, "A" and "B" respectively indicate the row and first column addresses
53 being latched into the RAM (on a negative edge for ~RAS and ~CAS
54 respectively), and "C" indicates the second column address being latched into
55 the RAM. Presumably, the first and second half-bytes can be read at "F" and
56 "S" respectively, and the row and column addresses must be made available at
57 "a" and "b" (and "c") respectively at the latest.
58
59 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
60 address access time of 90ns (maximum), which appears to mean that
61 approximately two 16MHz cycles after the row address is latched, and one and a
62 half cycles after the column address is latched, the data becomes available.
63
64 Note that the Service Manual refers to the negative edge of RAS and CAS, but
65 the datasheet for the similar TM4164EC4 product shows latching on the negative
66 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
67 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
68 "page mode" provides the appropriate behaviour for that particular product.
69
70 See: Acorn Electron Advanced User Guide
71 See: Acorn Electron Service Manual
72 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
73 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
74
75 Video Timing
76 ------------
77
78 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
79 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
80 (including the "colour burst"), and 1.65µs for the "front porch", totalling
81 12.05µs and thus leaving 51.95µs for the active video signal for each
82 scanline. As the Service Manual suggests in the oscilloscope traces, the
83 display information is transmitted more or less centred within the active
84 video period since the ULA will only be providing pixel data for 40µs in each
85 scanline.
86
87 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
88 each scanline can be divided into 1024 cycles, although only 640 at most are
89 actively used to provide pixel data. Pixel data production should only occur
90 within a certain period on each scanline, approximately 262 cycles after the
91 start of hsync:
92
93 active video period = 51.95µs
94 pixel data period = 40µs
95 total silent period = 51.95µs - 40µs = 11.95µs
96 silent periods (before and after) = 11.95µs / 2 = 5.975µs
97 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
98 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
99 pixel data period start cycle = 16.375µs / 62.5ns = 262
100
101 By choosing a number divisible by 8, the RAM access mechanism can be
102 synchronised with the pixel production. Thus, 264 is a more appropriate start
103 cycle.
104
105 The "vertical blanking period", meaning the period before picture information
106 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
107 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
108 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
109 occurs half way through the 23rd scanline period measured from the start of
110 vsync:
111
112 10 20 23
113 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
114 Line from 1: 0 22 3
115 Line on screen: .:::::VVVVV::::: 12233445566
116 |_________________________________________________|
117 25 line vertical blanking period
118
119 In the second field of a frame, the first visible scanline coincides with the
120 24th scanline period measured from the start of line 313 in the frame:
121
122 310 336
123 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
124 Line from 313: 0 23
125 Line on screen: 88:::::VVVVV:::: 11223344
126 288 | |
127 |_________________________________________________|
128 25 line vertical blanking period
129
130 In order to consider only full lines, we might consider the start of each
131 frame to occur 23 lines after the start of vsync.
132
133 Again, it is likely that pixel data production should only occur on scanlines
134 within a certain period on each frame. The "625/50" document indicates that
135 only a certain region is "safe" to use, suggesting a vertically centred region
136 with approximately 15 blank lines above and below the picture. Thus, the start
137 of the picture could be chosen as 38 lines after the start of vsync.
138
139 See: http://en.wikipedia.org/wiki/PAL
140 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
141 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
142 http://lipas.uwasa.fi/~f76998/video/modes/
143 See: PAL TV timing and voltages
144 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
145 See: Line Standards
146 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
147
148 RAM Integrated Circuits
149 -----------------------
150
151 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
152 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
153 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
154 have 16 pins and address 65536 bits through a 1-bit wide channel.
155
156 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
157 the Samsung-produced KM41464 series is apparently equivalent to the Texas
158 Instruments 4164 chips presumably used in the Electron.
159
160 The TM4164EC4 series combines 4 64K x 1b units into a single package and
161 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
162 (in the Advanced User Guide but not the Service Manual), and it also has 22
163 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
164 of the individual 4164-15 modules, presumably allowing concurrent access to
165 the packaged memory units.
166
167 As far as currently available replacements are concerned, the NTE4164 is a
168 potential candidate: according to the Vetco Electronics entry, it is
169 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
170 parts include the NTE2164 and the NTE6664, both of which appear to have
171 largely the same performance and connection characteristics. Meanwhile, the
172 NTE21256 appears to be a 16-pin replacement with four times the capacity that
173 maintains the single data input and output pins. Using the NTE21256 as a
174 replacement for all ICs combined would be difficult because of the single bit
175 output.
176
177 Another device equivalent to the 4164-15 appears to be available under the
178 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
179 site lists data sheets for other devices on the same page, but these are
180 different and actually appear to be provided under the 41574 product code (but
181 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
182 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
183 employing 4 pins for both input and output.
184
185 Pins I/O pins Row access Column access
186 ---- -------- ---------- -------------
187 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
188 KM41464AP 18 4 150ns (15) 75ns (15)
189 NTE21256 16 1 + 1 150ns 75ns
190 HYB 4164-2 16 1 + 1 150ns 100ns
191 µPD41464 18 4 120ns (12) 60ns (12)
192
193 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
194 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
195 See: Dynamic RAMS
196 http://www.unicornelectronics.com/IC/DYNAMIC.html
197 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
198 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
199 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
200 http://www.vetco.net/catalog/product_info.php?products_id=2806
201 See: NTE4164 - IC-NMOS 64K DRAM 150NS
202 http://www.vetco.net/catalog/product_info.php?products_id=3680
203 See: NTE21256 - IC-256K DRAM 150NS
204 http://www.vetco.net/catalog/product_info.php?products_id=2799
205 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
206 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
207 See: NTE6664 - IC-MOS 64K DRAM 150NS
208 http://www.vetco.net/catalog/product_info.php?products_id=5213
209 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
210 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
211 See: 4164-150: MAJOR BRANDS
212 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
213 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
214 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
215 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
216 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
217 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
218 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
219 See: 41464-10: MAJOR BRANDS
220 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
221
222 Interrupts
223 ----------
224
225 The ULA generates IRQs (maskable interrupts) according to certain conditions
226 and these conditions are controlled by location &FE00:
227
228 * Vertical sync (bottom of displayed screen)
229 * 50MHz real time clock
230 * Transmit data empty
231 * Receive data full
232 * High tone detect
233
234 The ULA is also used to clear interrupt conditions through location &FE05. Of
235 particular significance is bit 7, which must be set if an NMI (non-maskable
236 interrupt) has occurred and has thus suspended ULA access to memory, restoring
237 the normal function of the ULA.
238
239 ROM Paging
240 ----------
241
242 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
243 mappings exist:
244
245 8 keyboard
246 9 keyboard (duplicate)
247 10 BASIC ROM
248 11 BASIC ROM (duplicate)
249
250 Paging in a ROM involves the following procedure:
251
252 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
253 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
254 selected.
255 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
256 whilst writing the desired ROM number n in bits 0 to 2.
257
258 Shadow/Expanded Memory
259 ----------------------
260
261 The Electron exposes all sixteen address lines and all eight data lines
262 through the expansion bus. Using such lines, it is possible to provide
263 additional memory - typically sideways ROM and RAM - on expansion cards and
264 through cartridges, although the official cartridge specification provides
265 fewer address lines and only seeks to provide access to memory in 16K units.
266
267 Various modifications and upgrades were developed to offer "turbo"
268 capabilities to the Electron, permitting the CPU to access a separate 8K of
269 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
270 the ULA through additional logic. However, an enhanced ULA might support
271 independent CPU access to memory over the expansion bus by allowing itself to
272 be discharged from providing access to memory, potentially for a range of
273 addresses, and for the CPU to communicate with external memory uninterrupted.
274
275 Hardware Scrolling
276 ------------------
277
278 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
279 the least significant 5 bits being zero, thus limiting the scrolling
280 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
281 using the same layout of these addresses.
282
283 |--&FE02--------------| |--&FE03--------------|
284 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
285
286 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
287
288 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
289 memory to pixel locations is character oriented. A change in 8 bytes would
290 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
291 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
292 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
293 Guide).
294
295 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
296 of changing the screen address by 2 bytes is the change in the number of lines
297 from the initial and final character rows that need reading by the ULA, which
298 would need to maintain this state information (although this is a relatively
299 trivial change). Another pitfall is the complication that might be introduced
300 to software writing bitmaps of character height to the screen.
301
302 Enhancement: Region Blanking
303 ----------------------------
304
305 The problem of permitting character-oriented blitting in programs whilst
306 scrolling the screen by sub-character amounts could be mitigated by permitting
307 a region of the display to be blank, such as the final lines of the display.
308 Consider the following vertical scrolling by 2 bytes that would cause an
309 initial character row of 6 lines and a final character row of 2 lines:
310
311 6 lines - initial, partial character row
312 248 lines - 31 complete rows
313 2 lines - final, partial character row
314
315 If a routine were in use that wrote 8 line bitmaps to the partial character
316 row now split in two, it would be advisable to hide one of the regions in
317 order to prevent content appearing in the wrong place on screen (such as
318 content meant to appear at the top "leaking" onto the bottom). Blanking 6
319 lines would be sufficient, as can be seen from the following cases.
320
321 Scrolling up by 2 lines:
322
323 6 lines - initial, partial character row
324 240 lines - 30 complete rows
325 4 lines - part of 1 complete row
326 -----------------------------------------------------------------
327 4 lines - part of 1 complete row (hidden to maintain 250 lines)
328 2 lines - final, partial character row (hidden)
329
330 Scrolling down by 2 lines:
331
332 2 lines - initial, partial character row
333 248 lines - 31 complete rows
334 ----------------------------------------------------------
335 6 lines - final, partial character row (hidden)
336
337 Thus, in this case, region blanking would impose a 250 line display with the
338 bottom 6 lines blank.
339
340 See the description of the display suspend enhancement for a more efficient
341 way of blanking lines whilst allowing the CPU to perform useful work during
342 the blanking period.
343
344 Enhancement: Screen Height Adjustment
345 -------------------------------------
346
347 The height of the screen could be configurable in order to reduce screen
348 memory consumption. This is not quite done in MODE 3 and 6 since the start of
349 the screen appears to be rounded down to the nearest page, but by reducing the
350 height by amounts more than a page, savings would be possible. For example:
351
352 Screen width Depth Height Bytes per line Saving in bytes Start address
353 ------------ ----- ------ -------------- --------------- -------------
354 640 1 252 80 320 &3140 -> &3100
355 640 1 248 80 640 &3280 -> &3200
356 320 1 240 40 640 &5A80 -> &5A00
357 320 2 240 80 1280 &3500
358
359 Screen Mode Selection
360 ---------------------
361
362 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
363 range of modes, the other bits of &FE*7 (related to sound, cassette
364 input/output and the Caps Lock LED) would need to be reassigned and bit 0
365 potentially being made available for use.
366
367 Enhancement: Palette Definition
368 -------------------------------
369
370 Since all memory accesses go via the ULA, an enhanced ULA could employ more
371 specific addresses than &FE*X to perform enhanced functions. For example, the
372 palette control is done using &FE*8-F and merely involves selecting predefined
373 colours, whereas an enhanced ULA could support the redefinition of all 16
374 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
375 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
376 specifications similar to those used on the Archimedes.
377
378 The principal limitation here is actually the hardware: the Electron has only
379 a single output line for each of the red, green and blue channels, and if
380 those outputs are strictly digital and can only be set to a "high" and "low"
381 value, then only the existing eight colours are possible. If a modern ULA were
382 able to output analogue values, it would still need to be assessed whether the
383 circuitry could successfully handle and propagate such values. Various sources
384 indicate that only "TTL levels" are supported by the RGB output circuit, and
385 since there are 74LS08 AND logic gates involved in the RGB component outputs
386 from the ULA, it is likely that the ULA is expected to provide only "high" or
387 "low" values.
388
389 Short of adding extra outputs from the ULA (either additional red, green and
390 blue outputs or a combined intensity output), another approach might involve
391 some kind of modulation where an output value might be encoded in multiple
392 pulses at a higher frequency than the pixel frequency. However, this would
393 demand additional circuitry outside the ULA, and component RGB monitors would
394 probably not be able to take advantage of this feature; only UHF and composite
395 video devices (the latter with the composite video colour support enabled on
396 the Electron's circuit board) would potentially benefit.
397
398 Flashing Colours
399 ----------------
400
401 According to the Advanced User Guide, "The cursor and flashing colours are
402 entirely generated in software: This means that all of the logical to physical
403 colour map must be changed to cause colours to flash." This appears to suggest
404 that the palette registers must be updated upon the flash counter - read and
405 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
406 colour pairs to be any combination of colours might be possible, instead of
407 having colour complements as pairs.
408
409 It is conceivable that the interrupt code responsible does the simple thing
410 and merely inverts the current values for any logical colours (LC) for which
411 the associated physical colour (as supplied as the second parameter to the VDU
412 19 call) has the top bit of its four bit value set. These top bits are not
413 recorded in the palette registers but are presumably recorded separately and
414 used to build bitmaps as follows:
415
416 LC 2 colour 4 colour 16 colour 4-bit value for inversion
417 -- -------- -------- --------- -------------------------
418 0 00010001 00010001 00010001 1, 1, 1
419 1 01000100 00100010 00010001 4, 2, 1
420 2 01000100 00100010 4, 2
421 3 10001000 00100010 8, 2
422 4 00010001 1
423 5 00010001 1
424 6 00100010 2
425 7 00100010 2
426 8 01000100 4
427 9 01000100 4
428 10 10001000 8
429 11 10001000 8
430 12 01000100 4
431 13 01000100 4
432 14 10001000 8
433 15 10001000 8
434
435 Inversion value calculation:
436
437 2 colour formula: 1 << (colour * 2)
438 4 colour formula: 1 << colour
439 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
440
441 For example, where logical colour 0 has been mapped to a physical colour in
442 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
443 the inversion operation. (The lower three bits of the physical colour would be
444 used to set the underlying colour information affected by the inversion
445 operation.)
446
447 An operation in the interrupt code would then combine the bitmaps for all
448 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
449 combined for groups of logical colours as follows:
450
451 Logical colours
452 ---------------
453 0, 2, 8, 10
454 4, 6, 12, 14
455 5, 7, 13, 15
456 1, 3, 9, 11
457
458 These combined bitmaps would be EORed with the existing palette register
459 values in order to perform the value inversion necessary to produce the
460 flashing effect.
461
462 Thus, in the VDU 19 operation, the appropriate inversion value would be
463 calculated for the logical colour, and this value would then be combined with
464 other inversion values in a dedicated memory location corresponding to the
465 colour's group as indicated above. Meanwhile, the palette channel values would
466 be derived from the lower three bits of the specified physical colour and
467 combined with other palette data in dedicated memory locations corresponding
468 to the palette registers.
469
470 Enhancement: Palette Definition Lists
471 -------------------------------------
472
473 It can be useful to redefine the palette in order to change the colours
474 available for a particular region of the screen, particularly in modes where
475 the choice of colours is constrained, and if an increased colour depth were
476 available, palette redefinition would be useful to give the illusion of more
477 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
478 by using interrupt-driven timers, but a more efficient approach would involve
479 presenting lists of palette definitions to the ULA so that it can change the
480 palette at a particular display line.
481
482 One might define a palette redefinition list in a region of memory and then
483 communicate its contents to the ULA by writing the address and length of the
484 list, along with the display line at which the palette is to be changed, to
485 ULA registers such that the ULA buffers the list and performs the redefinition
486 at the appropriate time. Throughput/bandwidth considerations might impose
487 restrictions on the practical length of such a list, however.
488
489 Enhancement: Palette-Free Modes
490 -------------------------------
491
492 Palette-free modes might be defined where bit values directly correspond to
493 the red, green and blue channels, although this would mostly make sense only
494 for modes with depths greater than the standard 4 bits per pixel, and such
495 modes would require more memory than MODE 2 if they were to have an acceptable
496 resolution.
497
498 Enhancement: Display Suspend
499 ----------------------------
500
501 Especially when writing to the screen memory, it could be beneficial to be
502 able to suspend the ULA's access to the memory, instead producing blank values
503 for all screen pixels until a program is ready to reveal the screen. This is
504 different from palette blanking since with a blank palette, the ULA is still
505 reading screen memory and translating its contents into pixel values that end
506 up being blank.
507
508 This function is reminiscent of a capability of the ZX81, albeit necessary on
509 that hardware to reduce the load on the system CPU which was responsible for
510 producing the video output. By allowing display suspend on the Electron, the
511 performance benefit would be derived from giving the CPU full access to the
512 memory bandwidth.
513
514 Enhancement: Memory Filling
515 ---------------------------
516
517 A capability that could be given to an enhanced ULA is that of permitting the
518 ULA to write to screen memory as well being able to read from it. Although
519 such a capability would probably not be useful in conjunction with the
520 existing read operations when producing a screen display, and insufficient
521 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
522 capability could be offered during a display suspend period (as described
523 above), permitting a more efficient mechanism to rapidly fill memory with a
524 predetermined value.
525
526 This capability could also support block filling, where the limits of the
527 filled memory would be defined by the position and size of a screen area,
528 although this would demand the provision of additional registers in the ULA to
529 retain the details of such areas and additional logic to control the fill
530 operation.
531
532 Enhancement: Hardware Sprites
533 -----------------------------
534
535 An enhanced ULA might provide hardware sprites, but this would be done in an
536 way that is incompatible with the standard ULA, since no &FE*X locations are
537 available for allocation. To keep the facility simple, hardware sprites would
538 have a standard byte width and height.
539
540 The specification of sprites could involve the reservation of 16 locations
541 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
542 location pair referring to the sprite data. By limiting the ULA to dealing
543 with a fixed number of sprites, the work required inside the ULA would be
544 reduced since it would avoid having to deal with arbitrary numbers of sprites.
545
546 The principal limitation on providing hardware sprites is that of having to
547 obtain sprite data, given that the ULA is usually required to retrieve screen
548 data, and given the lack of memory bandwidth available to retrieve sprite data
549 (particularly from multiple sprites supposedly at the same position) and
550 screen data simultaneously. Although the ULA could potentially read sprite
551 data and screen data in alternate memory accesses in screen modes where the
552 bandwidth is not already fully utilised, this would result in a degradation of
553 performance.
554
555 Enhancement: Additional Screen Mode Configurations
556 --------------------------------------------------
557
558 Alternative screen mode configurations could be supported. The ULA has to
559 produce 640 pixel values across the screen, with pixel doubling or quadrupling
560 employed to fill the screen width:
561
562 Screen width Columns Scaling Depth Bytes
563 ------------ ------- ------- ----- -----
564 640 80 x1 1 80
565 320 40 x2 1, 2 40, 80
566 160 20 x4 2, 4 40, 80
567
568 It must also use at most 80 byte-sized memory accesses to provide the
569 information for the display. Given that characters must occupy an 8x8 pixel
570 array, if a configuration featuring anything other than 20, 40 or 80 character
571 columns is to be supported, compromises must be made such as the introduction
572 of blank pixels either between characters (such as occurs between rows in MODE
573 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
574 in MODE 3 and 6). Consider the following configuration:
575
576 Screen width Columns Scaling Depth Bytes Blank
577 ------------ ------- ------- ----- ------ -----
578 208 26 x3 1, 2 26, 52 16
579
580 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
581 colours could be provided, with 16 blank pixel values (out of a total of 640)
582 generated either at the start or end (or split between the start and end) of
583 each scanline.
584
585 Enhancement: Character Attributes
586 ---------------------------------
587
588 The BBC Micro MODE 7 employs something resembling character attributes to
589 support teletext displays, but depends on circuitry providing a character
590 generator. The ZX Spectrum, on the other hand, provides character attributes
591 as a means of colouring bitmapped graphics. Although such a feature is very
592 limiting as the sole means of providing multicolour graphics, in situations
593 where the choice is between low resolution multicolour graphics or high
594 resolution monochrome graphics, character attributes provide a potentially
595 useful compromise.
596
597 For each byte read, the ULA must deliver 8 pixel values (out of a total of
598 640) to the video output, doing so by either emptying its pixel buffer on a
599 pixel per cycle basis, or by multiplying pixels and thus holding them for more
600 than one cycle. For example for a screen mode having 640 pixels in width:
601
602 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
603 Reads: B B
604 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
605
606 And for a screen mode having 320 pixels in width:
607
608 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
609 Reads: B
610 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
611
612 However, in modes where less than 80 bytes are required to generate the pixel
613 values, an enhanced ULA might be able to read additional bytes between those
614 providing the bitmapped graphics data:
615
616 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
617 Reads: B A
618 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
619
620 These additional bytes could provide colour information for the bitmapped data
621 in the following character column (of 8 pixels). Since it would be desirable
622 to apply attribute data to the first column, the initial 8 cycles might be
623 configured to not produce pixel values.
624
625 For an entire character, attribute data need only be read for the first row of
626 pixels for a character. The subsequent rows would have attribute information
627 applied to them, although this would require the attribute data to be stored
628 in some kind of buffer. Thus, the following access pattern would be observed:
629
630 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
631
632 A whole byte used for colour information for a whole character would result in
633 a choice of 256 colours, and this might be somewhat excessive. By only reading
634 attribute bytes at every other opportunity, a choice of 16 colours could be
635 applied individually to two characters.
636
637 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
638 Reads: B A B -
639 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
640
641 Further reductions in attribute data access, offering 4 colours for every
642 character in a four character block, for example, might also be worth
643 considering.
644
645 Consider the following configurations for screen modes with a colour depth of
646 1 bit per pixel for bitmap information:
647
648 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
649 ------------ ------- ------- --------- --------- ------- ------------
650 320 40 x2 40 40 256 &5300
651 320 40 x2 40 20 16 &5580 -> &5500
652 320 40 x2 40 10 4 &56C0 -> &5600
653 208 26 x3 26 26 256 &62C0 -> &6200
654 208 26 x3 26 13 16 &6460 -> &6400
655
656 Enhancement: MODE 7 Emulation using Character Attributes
657 --------------------------------------------------------
658
659 If the scheme of applying attributes to character regions were employed to
660 emulate MODE 7, in conjunction with the MODE 6 display technique, the
661 following configuration would be required:
662
663 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
664 ------------ ------- ---- --------- --------- ------- ------------
665 320 40 25 40 20 16 &5ECC -> &5E00
666 320 40 25 40 10 4 &5FC6 -> &5F00
667
668 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
669 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
670 at least make a limited 40-column multicolour mode available as a substitute
671 for MODE 7.
672
673 Enhancement: High Resolution Graphics and Mode Layouts
674 ------------------------------------------------------
675
676 Screen modes with different screen memory mappings, higher resolutions and
677 larger colour depths might be possible, but this would in most cases involve
678 the allocation of more screen memory, and the ULA would probably then be
679 obliged to page in such memory for the CPU to be able to sensibly access it
680 all. Merely changing the memory mappings in order to have Archimedes-style
681 row-oriented screen addresses (instead of character-oriented addresses) could
682 be done for the existing modes, but this might not be sufficiently beneficial,
683 especially since accessing regions of the screen would involve incrementing
684 pointers by amounts that are inconvenient on an 8-bit CPU.
685
686 Enhancement: Genlock Support
687 ----------------------------
688
689 The ULA generates a video signal in conjunction with circuitry producing the
690 output features necessary for the correct display of the screen image.
691 However, it appears that the ULA drives the video synchronisation mechanism
692 instead of reacting to an existing signal. Genlock support might be possible
693 if the ULA were made to be responsive to such external signals, resetting its
694 address generators upon receiving synchronisation events.
695
696 Enhancement: Improved Sound
697 ---------------------------
698
699 The standard ULA reserves &FE*6 for sound generation and cassette input/output
700 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
701 cassette I/O), thus making it impossible to support multiple channels within
702 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
703 and an enhanced ULA could adopt this interface.
704
705 The BBC Micro uses the SN76489 chip to produce sound, and the entire
706 functionality of this chip could be emulated for enhanced sound, with a subset
707 of the functionality exposed via the &FE*6 interface.
708
709 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
710
711 Enhancement: Waveform Upload
712 ----------------------------
713
714 As with a hardware sprite function, waveforms could be uploaded or referenced
715 using locations as registers referencing memory regions.
716
717 Enhancement: Sound Input/Output
718 -------------------------------
719
720 Since the ULA already controls audio input/output for cassette-based data, it
721 would have been interesting to entertain the idea of sampling and output of
722 sounds through the cassette interface. However, a significant amount of
723 circuitry is employed to process the input signal for use by the ULA and to
724 process the output signal for recording.
725
726 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
727
728 Enhancement: BBC ULA Compatibility
729 ----------------------------------
730
731 Although some new ULA functions could be defined in a way that is also
732 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
733 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
734 map, but controls various functions specific to the 6845 video controller;
735 &FE08-F is reserved for the serial controller. It therefore becomes possible
736 to disregard compatibility where compatibility is already disregarded for a
737 particular area of functionality.
738
739 &FE20-F maps to video ULA functionality on the BBC Micro which provides
740 control over the palette (using address &FE21, compared to &FE07-F on the
741 Electron) and other system-specific functions. Since the location usage is
742 generally incompatible, this region could be reused for other purposes.
743
744 Enhancement: Increased RAM, ULA and CPU Performance
745 ---------------------------------------------------
746
747 More modern implementations of the hardware might feature faster RAM coupled
748 with an increased ULA clock frequency in order to increase the bandwidth
749 available to the ULA and to the CPU in situations where the ULA is not needed
750 to perform work. A ULA employing a 32MHz clock would be able to complete the
751 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
752 to access the RAM for the following 250ns even in display modes requiring the
753 retrieval of a byte for the display every 500ns. The CPU could, subject to
754 timing issues, run at 2MHz even in MODE 0, 1 and 2.
755
756 A scheme such as that described above would have a similar effect to the
757 scheme employed in the BBC Micro, although the latter made use of RAM with a
758 wider bandwidth in order to complete memory transfers within 250ns and thus
759 permit the CPU to run continuously at 2MHz.
760
761 Higher bandwidth could potentially be used to implement exotic features such
762 as RAM-resident hardware sprites or indeed any feature demanding RAM access
763 concurrent with the production of the display image.
764
765 ULA Pin Functions
766 -----------------
767
768 The functions of the ULA pins are described in the Electron Service Manual. Of
769 interest to video processing are the following:
770
771 CSYNC (low during horizontal or vertical synchronisation periods, high
772 otherwise)
773
774 HS (low during horizontal synchronisation periods, high otherwise)
775
776 RED, GREEN, BLUE (pixel colour outputs)
777
778 CLOCK IN (a 16MHz clock input, 4V peak to peak)
779
780 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
781
782 More general memory access pins:
783
784 RAM0...RAM3 (data lines to/from the RAM)
785
786 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
787
788 RAS (row address strobe setting the row address on a negative edge - see the
789 timing notes)
790
791 CAS (column address strobe setting the column address on a negative edge -
792 see the timing notes)
793
794 WE (sets write enable with logic 0, read with logic 1)
795
796 ROM (select data access from ROM)
797
798 CPU-oriented memory access pins:
799
800 A0...A15 (CPU address lines)
801
802 PD0...PD7 (CPU data lines)
803
804 R/W (indicates CPU write with logic 0, CPU read with logic 1)
805
806 Interrupt-related pins:
807
808 NMI (CPU request for uninterrupted 1MHz access to memory)
809
810 IRQ (signal event to CPU)
811
812 POR (power-on reset, resetting the ULA on a positive edge and asserting the
813 CPU's RST pin)
814
815 RST (master reset for the CPU signalled on power-up and by the Break key)
816
817 Keyboard-related pins:
818
819 KBD0...KBD3 (keyboard inputs)
820
821 CAPS LOCK (control status LED)
822
823 Sound-related pins:
824
825 SOUND O/P (sound output using internal oscillator)
826
827 Cassette-related pins:
828
829 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
830
831 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
832
833 CAS RC (detect high tone)
834
835 CAS MO (motor relay output)
836
837 ÷13 IN (~1200 baud clock input)
838
839 References
840 ----------
841
842 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm