ULA

Graph

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Added planar graphics display remarks. default tip
Added memory pricing details.
Added remarks about text mode screen sizes and memory layouts.
Moved the new section to be adjacent to a related section, adding some notes.
Added a suggested text mode approach.
Fixed CPU clock cycle scheduling, synchronising with memory signalling.
Refined the address timing details slightly.
Added notes about dual page mode transfers in each 2MHz cycle for an 8-bit RAM
Updated datasheet URL.
Added more 8-bit wide RAM access notes plus alternative keyboard matrix support.
Added more remarks about 8-bit wide RAM access.
Added Acorn dealer pricing note.
Added more RAM pricing data.
Added a note about 4MHz CPU/ULA memory access interleaving.
Added character generator support enhancement.
Expanded mode property relationship descriptions; introduced tables.
Added notes about mode numbering and selection in the ULA, suggesting an
Added more component pricing details and discussion.
Added notes about memory pricing and other machines using the 4164.
Added a note about the CPU performance limitations of suspending ULA RAM access.
Added notes on two-bytes-per-cycle ULA accesses and related considerations.
Added benchmark observations and a table of standard bandwidth characteristics.
Added clarifications about the use of 8MHz cycles with an 8-bit memory channel.
Added notes on 4164 RAM costs referencing historical remarks.
Added more remarks, particularly regarding direct CPU access to RAM.
Added remarks on 8-bit wide RAM access and possible 8MHz ULA frequency.
Added some memory bandwidth and architecture notes.
Added a note about keyboard access timings.
Added some notes about RAM access and the limitations applying to the CPU.
Made clarification about 1MHz RAM access, added 2MHz bandwidth figure.
Added some notes about video expansions and ULA simplification.
Noted that the ULA could re-read the character values and just increment an
Added notes about text-only modes, plus character and attribute value retrieval
Added CPU clock input and output notes.
Added a note about the CPU clock phases.
Added explicit reason for 2MHz RAM access not being feasible.
Introduced explicit next_frame calls after updating the screen start address.
Attempted to introduce hardware description language limitations, restructuring
Introduced a separate state-updating method and reordered methods.
Moved pixel generation to after the state update in the negative edge handler.
Moved video signalling into the negative edge handler in order to consolidate
Added notes about RAM access limitations preventing 2MHz RAM access by the CPU.
Removed the width instance attribute.
Moved address preparation onto negative edges and data acquisition onto positive
Shifted the timing states so that cycle 0 is aligned with the positive edge of
Refined and expanded the RAM access timings, moving data transfers to the
Renamed address to pixel_address.
Added initial CPU abstraction support together with read/write selection and
Made the next_vertical control-flow more hierarchical.
Introduced positive and negative signal transition update methods in order to
Tidied, introducing a write_pixels function, removing PIXEL_POSITIONS.
Fixed and tidied up pixel production, employing the general state counter for
Fixed the timing of pixel data decoding. Made the pixel data a plain integer.
Initialise the palette as red/green/blue triples.
Replaced the pixel buffer with translated byte data and a function converting
Changed the processing of pixel data and added remarks about pixel layout.
Replaced row spacing variables with row height and row offset variables.
Renamed reset methods and tidied slightly.
Separated address updating from the NMI-dependent RAM access condition.
Use the horizontal position counter by itself to manage the pixel buffer.
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