# HG changeset patch # User Paul Boddie # Date 1587068705 -7200 # Node ID 40c8c2cd15f49f90754e26715960135564c45d01 # Parent 62b4bf8a2511da8f2938769d4cb1d22d65d6e91f Added notes on two-bytes-per-cycle ULA accesses and related considerations. diff -r 62b4bf8a2511 -r 40c8c2cd15f4 ULA.txt --- a/ULA.txt Thu Apr 16 00:24:51 2020 +0200 +++ b/ULA.txt Thu Apr 16 22:25:05 2020 +0200 @@ -174,12 +174,49 @@ Another conceivable simplification from using an 8-bit wide RAM access channel with a single access within each 2MHz cycle is the possibility of allowing the CPU to signal directly to the RAM instead of having the ULA perform the access -signalling on the CPU's behalf. +signalling on the CPU's behalf. Note that it is this more leisurely signalling +that would allow the CPU to conduct accesses at 2MHz: the "compressed" +signalling being beyond the capabilities of the CPU. Note that 16MHz cycles would still be needed for the pixel clock in MODE 0, which needs to output eight pixels per 2MHz cycle, producing 640 monochrome pixels per 80-byte line. +An obvious consideration with regard to 8-bit wide access is whether the ULA +could still conduct the "compressed" signalling for its own RAM accesses: + + Time (ns): 0-------------- 500------------- ... + 2 MHz cycle: 0 1 ... + 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ... + /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ... + ~RAS: /---\___________/---\___________ ... + ~CAS: /-----\___/-\___/-----\___/-\___ ... +Address events: A B C A B C ... + Data events: 1 2 1 2 ... + + ~RAS ops: 1 0 1 0 ... + ~CAS ops: 1 0 1 0 1 0 1 0 ... + + Address ops: a b c a b c ... + Data ops: s f s f ... + + ~WE: ......W ... + PHI OUT: \_______/-------\_______/------- ... + CPU: L D L D ... + RnW: R R ... + +Here, "1" and "2" in the data events correspond to whole byte accesses, +effectively upgrading the half-byte "F" and "S" events in the existing ULA +arrangement. + +Although the provision of access for the CPU would adhere to the relevant +timing constraints, providing only one byte per 2MHz cycle, the ULA could +obtain two bytes per cycle. This would then free up bandwidth for the CPU in +screen modes where the ULA would normally be dominant (MODE 0 to 3), albeit at +the cost of extra buffering. Such buffering could also be done for modes where +the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into +single cycles and freeing up an extra cycle for CPU accesses. + CPU Clock Notes --------------- @@ -721,11 +758,38 @@ Unfortunately, the mechanism for accessing the RAM is too slow to provide data within the time constraints of 2MHz operation. There is no time remaining in a 2MHz cycle for the CPU to receive and process any retrieved data once the -necessary signalling has been performed. The only way for the CPU to be able -to access the RAM quickly enough would be to do away with the double 4-bit -access mechanism and to have a single 8-bit channel to the memory. This would -require twice as many 1-bit RAM chips or a different kind of RAM chip, but it -would also potentially simplify the ULA. +necessary signalling has been performed. + +The only way for the CPU to be able to access the RAM quickly enough would be +to do away with the double 4-bit access mechanism and to have a single 8-bit +channel to the memory. This would require twice as many 1-bit RAM chips or a +different kind of RAM chip, but it would also potentially simplify the ULA. + +The section on 8-bit wide RAM access discusses the possibilities around +changing the memory architecture, also describing the possibility of ULA +accesses achieving two bytes per 2MHz cycle due to the doubling of the memory +channel, leaving every other access free for the CPU during the display period +in MODE 0 to 3... + + Standard display period: UUUUUUUU + Modified display period: UCUCUCUC + +...and consolidating accesses in MODE 4 to 6: + + Standard display period: UCUCUCUC + Modified display period: UCCCUCCC + +Together with the enhancements for non-display periods, such an "Enhanced+ ULA" +would perform as follows: + + Standard ULA Enhanced+ ULA % Total Bandwidth Speedup +MODE 0, 1, 2 9728 bytes 29696 bytes 24% -> 74% 3.1 +MODE 3 12288 bytes 32256 bytes 31% -> 81% 2.6 +MODE 4, 5 19968 bytes 34816 bytes 50% -> 87% 1.7 +MODE 6 19968 bytes 36096 bytes 50% -> 90% 1.8 + +Of course, the principal enhancement would be the wider memory channel, with +more buffering in the ULA being its contribution to this arrangement. Enhancement: Region Blanking ----------------------------