1.1 --- a/ULA.txt Wed Nov 11 01:33:16 2020 +0100
1.2 +++ b/ULA.txt Sat Mar 06 14:20:42 2021 +0100
1.3 @@ -217,6 +217,20 @@
1.4 the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into
1.5 single cycles and freeing up an extra cycle for CPU accesses.
1.6
1.7 +A further consideration is whether the CPU and ULA could access the memory on
1.8 +interleaved 4MHz cycles, thus replicating the arrangement used by the CPU and
1.9 +Video ULA on the BBC Micro. One potential obstacle is that the apparent 4MHz
1.10 +access rate employed by the ULA does not involve the complete process for
1.11 +accessing the RAM: upon setting up the address and issuing the ~RAS signal,
1.12 +the ULA is able to make a pair of column accesses on the same "row" of memory,
1.13 +effectively achieving an average access rate of 4MHz.
1.14 +
1.15 +However, if arbitrary pairs of column accesses were to be attempted, as would
1.16 +be required by CPU and ULA interleaving, the ~RAS signal would need to be
1.17 +re-issued with different addresses being set up. This would expand the time to
1.18 +access a memory location to beyond the period of a 4MHz cycle, making it
1.19 +impossible to employ interleaved accesses at such a rate.
1.20 +
1.21 CPU Clock Notes
1.22 ---------------
1.23