1.1 --- a/ULA.txt Fri Oct 14 17:01:47 2022 +0200
1.2 +++ b/ULA.txt Sun Oct 16 01:27:06 2022 +0200
1.3 @@ -61,7 +61,7 @@
1.4 accessing RAM) during transfers of screen data.
1.5
1.6 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
1.7 -by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
1.8 +by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
1.9 approximately 62.5ns. To access the memory, the following patterns
1.10 corresponding to 16MHz cycles are required:
1.11
1.12 @@ -77,7 +77,7 @@
1.13 ~RAS ops: 1 0 1 0 ...
1.14 ~CAS ops: 1 0 1 0 1 0 1 0 ...
1.15
1.16 - Address ops: a b c a b c ...
1.17 + Address ops: a.b. c. a.b. c. ...
1.18 Data ops: s f s f ...
1.19
1.20 ~WE: ......W ...
1.21 @@ -98,8 +98,10 @@
1.22 respectively), and "C" indicates the second column address being latched into
1.23 the RAM. Presumably, the first and second half-bytes can be read at "F" and
1.24 "S" respectively, and the row and column addresses must be made available at
1.25 -"a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
1.26 -"s" for the first and second half-bytes respectively.
1.27 +"a" and "b" (and "c") respectively at the latest. The TM4164EC4 datasheet
1.28 +suggests that the addresses can be made available as the ~RAS and ~CAS levels
1.29 +are brought low. Data can be read at "f" and "s" for the first and second
1.30 +half-bytes respectively.
1.31
1.32 For the CPU, "L" indicates the point at which an address is taken from the CPU
1.33 address bus, on a negative edge of PHI OUT, with "D" being the point at which