1.1 --- a/Electron.txt Sat Feb 01 18:01:55 2014 +0100
1.2 +++ b/Electron.txt Sat Feb 01 18:04:06 2014 +0100
1.3 @@ -59,11 +59,20 @@
1.4 possible to just "borrow" one of the chips in order to isolate 8K of RAM for
1.5 direct access by the CPU.
1.6
1.7 +Being able to disable the ULA's access to RAM for a period of time while also
1.8 +disabling the video signal, effectively achieving the same as blanking the
1.9 +palette, would be a very simple but useful enhancement that would speed up
1.10 +programs needing to render large amounts of non-real-time content to the
1.11 +screen.
1.12 +
1.13 Improving Display Capabilities
1.14 ------------------------------
1.15
1.16 Perhaps the simplest improvement to the display capabilities would be to
1.17 -permit the RGB output levels to "float" between the current TTL high and low
1.18 -states, presumably enforced by various circuits. This would permit the choice
1.19 -of colours beyond the primary and secondary colour selection at a cost of some
1.20 -extra palette bits in the ULA and an adjustment to the board circuitry.
1.21 +permit the RGB output levels to hold intermediate values between the current
1.22 +high and low states, presumably enforced by various circuits. This would
1.23 +permit the choice of colours beyond the primary and secondary colour selection
1.24 +at a cost of some extra palette bits in the ULA and an adjustment to the board
1.25 +circuitry and would only benefit UHF and colour composite video displays, but
1.26 +the latter limitation might not be a significant issue for the majority of the
1.27 +intended audience.
2.1 --- a/ULA.txt Sat Feb 01 18:01:55 2014 +0100
2.2 +++ b/ULA.txt Sat Feb 01 18:04:06 2014 +0100
2.3 @@ -45,16 +45,21 @@
2.4 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
2.5 ~RAS: 0 1 0 1 ...
2.6 ~CAS: 0 1 0 1 0 1 0 1 ...
2.7 - A B B A B B ...
2.8 + A B C A B C ...
2.9 F S F S ...
2.10 - a b b a b b ...
2.11 + a b c a b c ...
2.12
2.13 -Here, "A" indicates the row and column addresses being latched into the RAM
2.14 -(on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
2.15 -second column address being latched into the RAM. Presumably, the first and
2.16 -second half-bytes can be read at "F" and "S" respectively, and the row and
2.17 -column addresses must be made available at "a" and "b" respectively at the
2.18 -latest.
2.19 +Here, "A" and "B" respectively indicate the row and first column addresses
2.20 +being latched into the RAM (on a negative edge for ~RAS and ~CAS
2.21 +respectively), and "C" indicates the second column address being latched into
2.22 +the RAM. Presumably, the first and second half-bytes can be read at "F" and
2.23 +"S" respectively, and the row and column addresses must be made available at
2.24 +"a" and "b" (and "c") respectively at the latest.
2.25 +
2.26 +The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
2.27 +address access time of 90ns (maximum), which appears to mean that
2.28 +approximately two 16MHz cycles after the row address is latched, and one and a
2.29 +half cycles after the column address is latched, the data becomes available.
2.30
2.31 Note that the Service Manual refers to the negative edge of RAS and CAS, but
2.32 the datasheet for the similar TM4164EC4 product shows latching on the negative
2.33 @@ -143,8 +148,13 @@
2.34 RAM Integrated Circuits
2.35 -----------------------
2.36
2.37 +Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
2.38 +CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
2.39 +available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
2.40 +have 16 pins and address 65536 bits through a 1-bit wide channel.
2.41 +
2.42 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
2.43 -the Samsung-produced KM4164 series is apparently equivalent to the Texas
2.44 +the Samsung-produced KM41464 series is apparently equivalent to the Texas
2.45 Instruments 4164 chips presumably used in the Electron.
2.46
2.47 The TM4164EC4 series combines 4 64K x 1b units into a single package and
2.48 @@ -172,8 +182,18 @@
2.49 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
2.50 employing 4 pins for both input and output.
2.51
2.52 + Pins I/O pins Row access Column access
2.53 + ---- -------- ---------- -------------
2.54 +TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
2.55 +KM41464AP 18 4 150ns (15) 75ns (15)
2.56 +NTE21256 16 1 + 1 150ns 75ns
2.57 +HYB 4164-2 16 1 + 1 150ns 100ns
2.58 +µPD41464 18 4 120ns (12) 60ns (12)
2.59 +
2.60 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
2.61 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
2.62 +See: Dynamic RAMS
2.63 + http://www.unicornelectronics.com/IC/DYNAMIC.html
2.64 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
2.65 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
2.66 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
2.67 @@ -370,7 +390,10 @@
2.68 blue outputs or a combined intensity output), another approach might involve
2.69 some kind of modulation where an output value might be encoded in multiple
2.70 pulses at a higher frequency than the pixel frequency. However, this would
2.71 -demand additional circuitry outside the ULA.
2.72 +demand additional circuitry outside the ULA, and component RGB monitors would
2.73 +probably not be able to take advantage of this feature; only UHF and composite
2.74 +video devices (the latter with the composite video colour support enabled on
2.75 +the Electron's circuit board) would potentially benefit.
2.76
2.77 Flashing Colours
2.78 ----------------
2.79 @@ -484,7 +507,27 @@
2.80
2.81 This function is reminiscent of a capability of the ZX81, albeit necessary on
2.82 that hardware to reduce the load on the system CPU which was responsible for
2.83 -producing the video output.
2.84 +producing the video output. By allowing display suspend on the Electron, the
2.85 +performance benefit would be derived from giving the CPU full access to the
2.86 +memory bandwidth.
2.87 +
2.88 +Enhancement: Memory Filling
2.89 +---------------------------
2.90 +
2.91 +A capability that could be given to an enhanced ULA is that of permitting the
2.92 +ULA to write to screen memory as well being able to read from it. Although
2.93 +such a capability would probably not be useful in conjunction with the
2.94 +existing read operations when producing a screen display, and insufficient
2.95 +bandwidth would exist to do so in high-bandwidth screen modes anyway, the
2.96 +capability could be offered during a display suspend period (as described
2.97 +above), permitting a more efficient mechanism to rapidly fill memory with a
2.98 +predetermined value.
2.99 +
2.100 +This capability could also support block filling, where the limits of the
2.101 +filled memory would be defined by the position and size of a screen area,
2.102 +although this would demand the provision of additional registers in the ULA to
2.103 +retain the details of such areas and additional logic to control the fill
2.104 +operation.
2.105
2.106 Enhancement: Hardware Sprites
2.107 -----------------------------
3.1 --- a/ula.py Sat Feb 01 18:01:55 2014 +0100
3.2 +++ b/ula.py Sat Feb 01 18:04:06 2014 +0100
3.3 @@ -126,6 +126,33 @@
3.4 self.memory[i << 1] = value >> 4
3.5 self.memory[i << 1 | 0x1] = value & 0xf
3.6
3.7 +class ShiftRegister:
3.8 +
3.9 + """
3.10 + A class representing a shift register, used for the internal state of the
3.11 + ULA within each 2MHz period.
3.12 + """
3.13 +
3.14 + def __init__(self):
3.15 + self.state = [0] * 8
3.16 + self.input = 0
3.17 +
3.18 + def set_input(self, input):
3.19 + self.input = input
3.20 +
3.21 + def shift(self):
3.22 +
3.23 + # NOTE: This is not meant to be "nice" Python, but instead models the
3.24 + # NOTE: propagation of state through the latches.
3.25 +
3.26 + self.state[0], self.state[1], self.state[2], self.state[3], \
3.27 + self.state[4], self.state[5], self.state[6], self.state[7] = \
3.28 + self.input, self.state[0], self.state[1], self.state[2], \
3.29 + self.state[3], self.state[4], self.state[5], self.state[6]
3.30 +
3.31 + def __getitem__(self, i):
3.32 + return self.state[i]
3.33 +
3.34 class ULA:
3.35
3.36 """
3.37 @@ -173,13 +200,16 @@
3.38
3.39 # Internal state.
3.40
3.41 - self.cycle = [0]*8 # counter within each 2MHz period represented by 8 latches
3.42 self.access = 0 # counter used to determine whether a byte needs reading
3.43 self.have_pixels = 0 # whether pixel data has been read
3.44 self.writing_pixels = 0 # whether pixel data can be written
3.45 self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data
3.46
3.47 - self.cycle[7] = 1 # assert the final latch (asserting the first on update)
3.48 + self.cycle = ShiftRegister() # 8-state counter within each 2MHz period
3.49 +
3.50 + self.cycle.set_input(1) # assert the input to set the first state output
3.51 + self.cycle.shift()
3.52 + self.cycle.set_input(0) # reset the input since only one state output will be active
3.53
3.54 self.reset_vertical()
3.55
3.56 @@ -323,15 +353,6 @@
3.57
3.58 access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
3.59
3.60 - # Update the state of the device.
3.61 - # NOTE: This is not meant to be "nice" Python, but instead models the
3.62 - # NOTE: propagation of state through the latches.
3.63 -
3.64 - self.cycle[0], self.cycle[1], self.cycle[2], self.cycle[3], \
3.65 - self.cycle[4], self.cycle[5], self.cycle[6], self.cycle[7] = \
3.66 - self.cycle[7], self.cycle[0], self.cycle[1], self.cycle[2], \
3.67 - self.cycle[3], self.cycle[4], self.cycle[5], self.cycle[6]
3.68 -
3.69 # Set row address (for ULA access only).
3.70
3.71 if self.cycle[0]:
3.72 @@ -434,6 +455,11 @@
3.73
3.74 self.access = (self.access + 1) % self.access_frequency
3.75
3.76 + # Update the state of the device.
3.77 +
3.78 + self.cycle.set_input(self.cycle[7])
3.79 + self.cycle.shift()
3.80 +
3.81
3.82
3.83 # Video signalling.