1.1 --- a/ULA.txt Sun Sep 04 00:59:40 2016 +0200
1.2 +++ b/ULA.txt Mon Nov 14 18:18:37 2016 +0100
1.3 @@ -120,6 +120,17 @@
1.4 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.5 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
1.6
1.7 +CPU Clock Notes
1.8 +---------------
1.9 +
1.10 +"The 6502 has a synchronous memory bus where the master clock is divided into
1.11 +two phases (Phase 1 and Phase 2). The address is always generated during Phase
1.12 +1 and all memory accesses take place during Phase 2."
1.13 +
1.14 +Thus, the inverse of PHI OUT provides the other phase of the clock.
1.15 +
1.16 +See: http://www.jmargolin.com/vgens/vgens.htm
1.17 +
1.18 Bandwidth Figures
1.19 -----------------
1.20