paul@0 | 1 | /* |
paul@0 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@35 | 22 | #include "vga.h" |
paul@0 | 23 | |
paul@0 | 24 | /* Disable JTAG functionality on pins. */ |
paul@0 | 25 | |
paul@0 | 26 | .section .devcfg0, "a" |
paul@0 | 27 | .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ |
paul@0 | 28 | |
paul@0 | 29 | /* |
paul@0 | 30 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
paul@21 | 31 | divided by 2, and FRCDIV+PLL selected. |
paul@0 | 32 | |
paul@0 | 33 | The watchdog timer (FWDTEN) is also disabled. |
paul@9 | 34 | |
paul@9 | 35 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
paul@9 | 36 | RPB4. |
paul@0 | 37 | */ |
paul@0 | 38 | |
paul@0 | 39 | .section .devcfg1, "a" |
paul@21 | 40 | .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; |
paul@9 | 41 | DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ |
paul@0 | 42 | |
paul@0 | 43 | /* |
paul@0 | 44 | Set the FRC oscillator PLL function with an input division of 4, an output |
paul@21 | 45 | division of 2, a multiplication of 24, yielding a multiplication of 3. |
paul@21 | 46 | |
paul@21 | 47 | The FRC is apparently at 16MHz and this produces a system clock of 48MHz. |
paul@0 | 48 | */ |
paul@0 | 49 | |
paul@0 | 50 | .section .devcfg2, "a" |
paul@21 | 51 | .word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; |
paul@21 | 52 | DEVCFG2<6:4> = FPLLMUL<2:0> = 111; |
paul@9 | 53 | DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ |
paul@0 | 54 | |
paul@0 | 55 | .text |
paul@0 | 56 | .globl _start |
paul@36 | 57 | .extern init_framebuffer |
paul@35 | 58 | .extern init_framebuffer_with_pattern |
paul@41 | 59 | .extern screendata |
paul@41 | 60 | .extern blit_string |
paul@80 | 61 | .extern message0 |
paul@80 | 62 | .extern message1 |
paul@0 | 63 | |
paul@78 | 64 | .macro load_affected |
paul@78 | 65 | lw $v0, -4($k0) |
paul@78 | 66 | lw $v1, -8($k0) |
paul@78 | 67 | lw $s0, -12($k0) |
paul@78 | 68 | lw $s1, -16($k0) |
paul@78 | 69 | lw $s2, -20($k0) |
paul@78 | 70 | lw $s3, -24($k0) |
paul@78 | 71 | lw $t8, -28($k0) |
paul@78 | 72 | lw $ra, -32($k0) |
paul@78 | 73 | lw $sp, -36($k0) |
paul@81 | 74 | lw $gp, -40($k0) |
paul@78 | 75 | .endm |
paul@78 | 76 | |
paul@78 | 77 | .macro load_state |
paul@78 | 78 | lw $s0, -44($k0) |
paul@78 | 79 | lw $s1, -48($k0) |
paul@78 | 80 | lw $s2, -52($k0) |
paul@78 | 81 | lw $s3, -56($k0) |
paul@81 | 82 | lw $gp, -60($k0) |
paul@78 | 83 | .endm |
paul@78 | 84 | |
paul@78 | 85 | .macro save_affected |
paul@78 | 86 | sw $v0, -4($k0) |
paul@78 | 87 | sw $v1, -8($k0) |
paul@78 | 88 | sw $s0, -12($k0) |
paul@78 | 89 | sw $s1, -16($k0) |
paul@78 | 90 | sw $s2, -20($k0) |
paul@78 | 91 | sw $s3, -24($k0) |
paul@78 | 92 | sw $t8, -28($k0) |
paul@78 | 93 | sw $ra, -32($k0) |
paul@78 | 94 | sw $sp, -36($k0) |
paul@81 | 95 | sw $gp, -40($k0) |
paul@78 | 96 | .endm |
paul@78 | 97 | |
paul@78 | 98 | .macro save_state |
paul@78 | 99 | sw $s0, -44($k0) |
paul@78 | 100 | sw $s1, -48($k0) |
paul@78 | 101 | sw $s2, -52($k0) |
paul@78 | 102 | sw $s3, -56($k0) |
paul@81 | 103 | sw $gp, -60($k0) |
paul@78 | 104 | .endm |
paul@78 | 105 | |
paul@0 | 106 | _start: |
paul@0 | 107 | /* |
paul@0 | 108 | Configure RAM. |
paul@0 | 109 | See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization |
paul@0 | 110 | */ |
paul@0 | 111 | |
paul@0 | 112 | la $v0, BMXCON |
paul@10 | 113 | lw $v1, 0($v0) |
paul@48 | 114 | |
paul@48 | 115 | /* Set zero wait states for address setup. */ |
paul@48 | 116 | |
paul@10 | 117 | li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */ |
paul@10 | 118 | and $v1, $v1, $t8 |
paul@48 | 119 | |
paul@48 | 120 | /* Set bus arbitration mode. */ |
paul@48 | 121 | |
paul@10 | 122 | li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */ |
paul@10 | 123 | ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */ |
paul@10 | 124 | and $v1, $v1, $t8 |
paul@10 | 125 | sw $v1, 0($v0) |
paul@0 | 126 | |
paul@0 | 127 | /* Enable caching. */ |
paul@0 | 128 | |
paul@14 | 129 | mfc0 $v1, CP0_CONFIG |
paul@14 | 130 | li $t8, ~CONFIG_K0 |
paul@14 | 131 | and $v1, $v1, $t8 |
paul@14 | 132 | ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT |
paul@14 | 133 | mtc0 $v1, CP0_CONFIG |
paul@0 | 134 | nop |
paul@0 | 135 | |
paul@0 | 136 | /* Get the RAM size. */ |
paul@0 | 137 | |
paul@3 | 138 | la $v0, BMXDRMSZ |
paul@18 | 139 | lw $t0, 0($v0) |
paul@0 | 140 | |
paul@0 | 141 | /* Initialise the stack pointer. */ |
paul@0 | 142 | |
paul@3 | 143 | li $v1, KSEG0_BASE |
paul@18 | 144 | addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ |
paul@9 | 145 | |
paul@0 | 146 | /* Initialise the globals pointer. */ |
paul@0 | 147 | |
paul@0 | 148 | lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 149 | ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 150 | |
paul@5 | 151 | /* Set pins for output. */ |
paul@0 | 152 | |
paul@0 | 153 | jal init_pins |
paul@0 | 154 | nop |
paul@0 | 155 | |
paul@15 | 156 | la $t0, PORTA |
paul@15 | 157 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@15 | 158 | sw $t1, CLR($t0) |
paul@15 | 159 | |
paul@77 | 160 | jal init_io_pins |
paul@5 | 161 | nop |
paul@5 | 162 | |
paul@0 | 163 | /* Initialise the status register. */ |
paul@0 | 164 | |
paul@0 | 165 | jal init_interrupts |
paul@0 | 166 | nop |
paul@0 | 167 | |
paul@18 | 168 | /* Initialise framebuffer. */ |
paul@18 | 169 | |
paul@36 | 170 | la $a0, screendata |
paul@36 | 171 | jal init_framebuffer |
paul@18 | 172 | nop |
paul@18 | 173 | |
paul@18 | 174 | sync |
paul@18 | 175 | |
paul@0 | 176 | /* Initialise timer. */ |
paul@0 | 177 | |
paul@4 | 178 | jal init_timer2 |
paul@0 | 179 | nop |
paul@0 | 180 | |
paul@3 | 181 | /* Initialise DMA. */ |
paul@3 | 182 | |
paul@3 | 183 | jal init_dma |
paul@3 | 184 | nop |
paul@3 | 185 | |
paul@15 | 186 | /* Initialise OC1 and OC2. */ |
paul@5 | 187 | |
paul@9 | 188 | jal init_oc |
paul@3 | 189 | nop |
paul@3 | 190 | |
paul@77 | 191 | /* Initialise UART for debugging. */ |
paul@77 | 192 | |
paul@77 | 193 | jal init_uart |
paul@77 | 194 | nop |
paul@77 | 195 | |
paul@34 | 196 | /* Initialise the display state. */ |
paul@34 | 197 | |
paul@34 | 198 | li $s0, 0 /* line counter */ |
paul@34 | 199 | la $s1, vbp_active /* current event */ |
paul@38 | 200 | li $s2, SCREEN_BASE /* line address */ |
paul@38 | 201 | li $s3, SCREEN_BASE /* screen address */ |
paul@38 | 202 | |
paul@38 | 203 | /* Save the state for retrieval in the interrupt handler. */ |
paul@38 | 204 | |
paul@38 | 205 | li $k0, IRQ_STACK_LIMIT |
paul@78 | 206 | save_state |
paul@34 | 207 | |
paul@0 | 208 | /* Enable interrupts and loop. */ |
paul@0 | 209 | |
paul@0 | 210 | jal enable_interrupts |
paul@0 | 211 | nop |
paul@0 | 212 | |
paul@0 | 213 | jal handle_error_level |
paul@0 | 214 | nop |
paul@0 | 215 | |
paul@3 | 216 | /* Main program. */ |
paul@3 | 217 | |
paul@39 | 218 | li $a1, (3 << 24) /* counter ~= 50000000 */ |
paul@39 | 219 | li $a2, 0xffffff /* test counter at every 1/4 of range */ |
paul@39 | 220 | move $t2, $zero /* picture to show */ |
paul@3 | 221 | |
paul@3 | 222 | /* Monitoring loop. */ |
paul@0 | 223 | loop: |
paul@3 | 224 | addiu $a1, $a1, -1 /* counter -= 1 */ |
paul@39 | 225 | and $t1, $a2, $a1 |
paul@39 | 226 | bnez $t1, loop |
paul@0 | 227 | nop |
paul@0 | 228 | |
paul@15 | 229 | la $t0, PORTA |
paul@15 | 230 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@3 | 231 | sw $t1, INV($t0) |
paul@0 | 232 | |
paul@77 | 233 | la $v0, U1TXREG |
paul@77 | 234 | li $v1, '.' |
paul@77 | 235 | sw $v1, 0($v0) |
paul@77 | 236 | |
paul@39 | 237 | bnez $a1, loop /* until counter == 0 */ |
paul@39 | 238 | nop |
paul@39 | 239 | |
paul@39 | 240 | bnez $t2, _picture1 |
paul@39 | 241 | nop |
paul@39 | 242 | |
paul@39 | 243 | /* Show picture 0. */ |
paul@39 | 244 | |
paul@39 | 245 | la $a0, screendata |
paul@39 | 246 | jal init_framebuffer |
paul@39 | 247 | nop |
paul@41 | 248 | |
paul@41 | 249 | la $a0, message0 |
paul@41 | 250 | li $a1, SCREEN_BASE_KSEG0 |
paul@41 | 251 | jal blit_string |
paul@41 | 252 | nop |
paul@41 | 253 | |
paul@39 | 254 | li $t2, 1 |
paul@39 | 255 | j _next |
paul@39 | 256 | nop |
paul@39 | 257 | |
paul@39 | 258 | _picture1: |
paul@39 | 259 | /* Show picture 1. */ |
paul@39 | 260 | |
paul@39 | 261 | jal init_framebuffer_with_pattern |
paul@39 | 262 | nop |
paul@41 | 263 | |
paul@41 | 264 | la $a0, message1 |
paul@41 | 265 | li $a1, SCREEN_BASE_KSEG0 |
paul@41 | 266 | jal blit_string |
paul@41 | 267 | nop |
paul@41 | 268 | |
paul@39 | 269 | move $t2, $zero |
paul@39 | 270 | |
paul@0 | 271 | _next: |
paul@39 | 272 | li $a1, (3 << 24) /* counter ~= 50000000 */ |
paul@39 | 273 | li $a2, 0xffffff /* test counter at every 1/4 of range */ |
paul@0 | 274 | j loop |
paul@0 | 275 | nop |
paul@0 | 276 | |
paul@0 | 277 | |
paul@0 | 278 | |
paul@0 | 279 | init_pins: |
paul@1 | 280 | /* DEVCFG0<2> needs setting to 0 before the program is run. */ |
paul@0 | 281 | |
paul@3 | 282 | la $v0, CFGCON |
paul@0 | 283 | li $v1, (1 << 3) /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 284 | sw $v1, CLR($v0) |
paul@0 | 285 | |
paul@3 | 286 | init_outputs: |
paul@3 | 287 | /* Remove analogue features from pins. */ |
paul@3 | 288 | |
paul@3 | 289 | la $v0, ANSELA |
paul@3 | 290 | sw $zero, 0($v0) /* ANSELA = 0 */ |
paul@3 | 291 | la $v0, ANSELB |
paul@3 | 292 | sw $zero, 0($v0) /* ANSELB = 0 */ |
paul@3 | 293 | |
paul@3 | 294 | la $v0, TRISA |
paul@3 | 295 | sw $zero, 0($v0) |
paul@0 | 296 | la $v0, TRISB |
paul@3 | 297 | sw $zero, 0($v0) |
paul@3 | 298 | |
paul@9 | 299 | la $v0, PORTA |
paul@9 | 300 | sw $zero, 0($v0) |
paul@9 | 301 | la $v0, PORTB |
paul@9 | 302 | sw $zero, 0($v0) |
paul@0 | 303 | |
paul@3 | 304 | jr $ra |
paul@0 | 305 | nop |
paul@0 | 306 | |
paul@0 | 307 | |
paul@0 | 308 | |
paul@0 | 309 | /* Initialisation routines. */ |
paul@0 | 310 | |
paul@4 | 311 | init_timer2: |
paul@0 | 312 | |
paul@49 | 313 | /* Initialise Timer2 for sync pulses. */ |
paul@0 | 314 | |
paul@4 | 315 | la $v0, T2CON |
paul@4 | 316 | sw $zero, 0($v0) /* T2CON = 0 */ |
paul@0 | 317 | nop |
paul@0 | 318 | |
paul@4 | 319 | la $v0, TMR2 |
paul@4 | 320 | sw $zero, 0($v0) /* TMR2 = 0 */ |
paul@5 | 321 | |
paul@4 | 322 | la $v0, PR2 |
paul@0 | 323 | li $v1, HFREQ_LIMIT |
paul@4 | 324 | sw $v1, 0($v0) /* PR2 = HFREQ_LIMIT */ |
paul@0 | 325 | |
paul@4 | 326 | /* Initialise Timer2 interrupt. */ |
paul@0 | 327 | |
paul@0 | 328 | la $v0, IFS0 |
paul@4 | 329 | li $v1, (1 << 9) |
paul@5 | 330 | sw $v1, CLR($v0) /* T2IF = 0 */ |
paul@5 | 331 | |
paul@4 | 332 | la $v0, IPC2 |
paul@5 | 333 | li $v1, 0b11111 |
paul@5 | 334 | sw $v1, CLR($v0) /* T2IP, T2IS = 0 */ |
paul@5 | 335 | li $v1, 0b11111 |
paul@5 | 336 | sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */ |
paul@5 | 337 | |
paul@0 | 338 | la $v0, IEC0 |
paul@4 | 339 | li $v1, (1 << 9) |
paul@5 | 340 | sw $v1, SET($v0) /* T2IE = 1 */ |
paul@0 | 341 | |
paul@0 | 342 | /* Start timer. */ |
paul@0 | 343 | |
paul@4 | 344 | la $v0, T2CON |
paul@5 | 345 | li $v1, (1 << 15) |
paul@5 | 346 | sw $v1, SET($v0) /* ON = 1 */ |
paul@5 | 347 | |
paul@5 | 348 | jr $ra |
paul@5 | 349 | nop |
paul@5 | 350 | |
paul@5 | 351 | |
paul@5 | 352 | |
paul@5 | 353 | /* |
paul@5 | 354 | Output compare initialisation. |
paul@5 | 355 | |
paul@15 | 356 | Timer2 will be used to trigger two events using OC1: one initiating the hsync |
paul@9 | 357 | pulse, and one terminating the pulse. The pulse should appear after the line |
paul@9 | 358 | data has been transferred using DMA, but this is achieved by just choosing |
paul@9 | 359 | suitable start and end values. |
paul@5 | 360 | |
paul@49 | 361 | Using OC2, Timer2 triggers a level shifting event and OC2 is reconfigured to |
paul@48 | 362 | reverse the level at a later point. In this way, the vsync pulse is generated |
paul@48 | 363 | and is synchronised to the display lines. |
paul@5 | 364 | */ |
paul@5 | 365 | |
paul@9 | 366 | init_oc: |
paul@15 | 367 | /* Disable OC1 interrupts. */ |
paul@9 | 368 | |
paul@9 | 369 | la $v0, IEC0 |
paul@15 | 370 | li $v1, (1 << 7) /* IEC0<7> = OC1IE = 0 */ |
paul@9 | 371 | sw $v1, CLR($v0) |
paul@9 | 372 | |
paul@9 | 373 | la $v0, IFS0 |
paul@15 | 374 | li $v1, (1 << 7) /* IFS0<7> = OC1IF = 0 */ |
paul@9 | 375 | sw $v1, CLR($v0) |
paul@9 | 376 | |
paul@15 | 377 | /* Initialise OC1. */ |
paul@9 | 378 | |
paul@15 | 379 | la $v0, OC1CON |
paul@15 | 380 | li $v1, 0b101 /* OC1CON<2:0> = OCM<2:0> = 101 (dual compare, continuous pulse) */ |
paul@9 | 381 | sw $v1, 0($v0) |
paul@9 | 382 | |
paul@9 | 383 | /* Pulse start and end. */ |
paul@9 | 384 | |
paul@15 | 385 | la $v0, OC1R |
paul@9 | 386 | li $v1, HSYNC_END /* HSYNC_START for positive polarity */ |
paul@9 | 387 | sw $v1, 0($v0) |
paul@9 | 388 | |
paul@15 | 389 | la $v0, OC1RS |
paul@9 | 390 | li $v1, HSYNC_START /* HSYNC_END for positive polarity */ |
paul@9 | 391 | sw $v1, 0($v0) |
paul@9 | 392 | |
paul@15 | 393 | /* OC1 is enabled. */ |
paul@9 | 394 | |
paul@15 | 395 | la $v0, OC1CON |
paul@9 | 396 | li $v1, (1 << 15) |
paul@9 | 397 | sw $v1, SET($v0) |
paul@9 | 398 | |
paul@9 | 399 | /* Disable OC2 interrupts. */ |
paul@5 | 400 | |
paul@5 | 401 | la $v0, IEC0 |
paul@5 | 402 | li $v1, (1 << 12) /* IEC0<12> = OC2IE = 0 */ |
paul@5 | 403 | sw $v1, CLR($v0) |
paul@5 | 404 | |
paul@5 | 405 | la $v0, IFS0 |
paul@5 | 406 | li $v1, (1 << 12) /* IFS0<12> = OC2IF = 0 */ |
paul@5 | 407 | sw $v1, CLR($v0) |
paul@5 | 408 | |
paul@5 | 409 | /* Initialise OC2. */ |
paul@5 | 410 | |
paul@5 | 411 | la $v0, OC2CON |
paul@9 | 412 | li $v1, 0b010 /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@5 | 413 | sw $v1, 0($v0) |
paul@5 | 414 | |
paul@9 | 415 | /* Set pulse position. */ |
paul@5 | 416 | |
paul@5 | 417 | la $v0, OC2R |
paul@9 | 418 | sw $zero, 0($v0) |
paul@5 | 419 | |
paul@9 | 420 | /* Enable OC2 later. */ |
paul@5 | 421 | |
paul@5 | 422 | jr $ra |
paul@5 | 423 | nop |
paul@5 | 424 | |
paul@77 | 425 | init_io_pins: |
paul@5 | 426 | /* Unlock the configuration register bits. */ |
paul@5 | 427 | |
paul@5 | 428 | la $v0, SYSKEY |
paul@5 | 429 | sw $zero, 0($v0) |
paul@5 | 430 | li $v1, 0xAA996655 |
paul@5 | 431 | sw $v1, 0($v0) |
paul@5 | 432 | li $v1, 0x556699AA |
paul@5 | 433 | sw $v1, 0($v0) |
paul@5 | 434 | |
paul@5 | 435 | la $v0, CFGCON |
paul@5 | 436 | lw $t8, 0($v0) |
paul@5 | 437 | li $v1, (1 << 13) /* IOLOCK = 0 */ |
paul@5 | 438 | sw $v1, CLR($v0) |
paul@5 | 439 | |
paul@15 | 440 | /* Map OC1 to RPA0. */ |
paul@9 | 441 | |
paul@15 | 442 | la $v0, RPA0R |
paul@15 | 443 | li $v1, 0b0101 /* RPA0R<3:0> = 0101 (OC1) */ |
paul@9 | 444 | sw $v1, 0($v0) |
paul@9 | 445 | |
paul@15 | 446 | /* Map OC2 to RPA1. */ |
paul@5 | 447 | |
paul@15 | 448 | la $v0, RPA1R |
paul@15 | 449 | li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */ |
paul@5 | 450 | sw $v1, 0($v0) |
paul@5 | 451 | |
paul@77 | 452 | /* Map U1TX to RPB15. */ |
paul@77 | 453 | |
paul@77 | 454 | la $v0, RPB15R |
paul@77 | 455 | li $v1, 0b0001 /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@77 | 456 | sw $v1, 0($v0) |
paul@77 | 457 | |
paul@5 | 458 | la $v0, CFGCON |
paul@5 | 459 | sw $t8, 0($v0) |
paul@5 | 460 | |
paul@5 | 461 | /* Lock the oscillator control register again. */ |
paul@5 | 462 | |
paul@5 | 463 | la $v0, SYSKEY |
paul@5 | 464 | li $v1, 0x33333333 |
paul@5 | 465 | sw $v1, 0($v0) |
paul@0 | 466 | |
paul@0 | 467 | jr $ra |
paul@0 | 468 | nop |
paul@1 | 469 | |
paul@1 | 470 | |
paul@1 | 471 | |
paul@5 | 472 | /* |
paul@5 | 473 | Direct Memory Access initialisation. |
paul@3 | 474 | |
paul@15 | 475 | Write 160 pixels to PORTB for the line data. This is initiated by a timer |
paul@9 | 476 | interrupt. Upon completion of the transfer, a DMA interrupt initiates the |
paul@9 | 477 | address update routine, changing the source address of the DMA channel. |
paul@3 | 478 | */ |
paul@3 | 479 | |
paul@3 | 480 | init_dma: |
paul@3 | 481 | /* Disable DMA interrupts. */ |
paul@1 | 482 | |
paul@3 | 483 | la $v0, IEC1 |
paul@59 | 484 | li $v1, (0b111 << 28) /* IEC1<30:28> = DMA2IE, DMA1IE, DMA0IE = 0 */ |
paul@3 | 485 | sw $v1, CLR($v0) |
paul@3 | 486 | |
paul@3 | 487 | /* Clear DMA interrupt flags. */ |
paul@1 | 488 | |
paul@3 | 489 | la $v0, IFS1 |
paul@59 | 490 | li $v1, (0b111 << 28) /* IFS1<30:28> = DMA2IF, DMA1IF, DMA0IF = 0 */ |
paul@3 | 491 | sw $v1, CLR($v0) |
paul@3 | 492 | |
paul@3 | 493 | /* Enable DMA. */ |
paul@3 | 494 | |
paul@3 | 495 | la $v0, DMACON |
paul@3 | 496 | li $v1, (1 << 15) |
paul@1 | 497 | sw $v1, SET($v0) |
paul@1 | 498 | |
paul@3 | 499 | /* |
paul@60 | 500 | Initialise a start channel. |
paul@60 | 501 | The start channel will be channel 0 (x = 0). |
paul@3 | 502 | |
paul@3 | 503 | Specify a priority of 3: |
paul@3 | 504 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@3 | 505 | |
paul@15 | 506 | Auto-enable the channel: |
paul@3 | 507 | DCHxCON<4> = CHAEN = 1 |
paul@3 | 508 | */ |
paul@3 | 509 | |
paul@3 | 510 | la $v0, DCH0CON |
paul@3 | 511 | li $v1, 0b10011 |
paul@3 | 512 | sw $v1, 0($v0) |
paul@3 | 513 | |
paul@5 | 514 | /* |
paul@60 | 515 | Initialise line and level reset channels. |
paul@60 | 516 | The line channel will be channel 1 (x = 1). |
paul@60 | 517 | The reset channel will be channel 2 (x = 2). |
paul@15 | 518 | |
paul@15 | 519 | Specify a priority of 3: |
paul@15 | 520 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@15 | 521 | |
paul@15 | 522 | Chain the channel to channel 0: |
paul@15 | 523 | DCHxCON<5> = CHCHN = 1 |
paul@15 | 524 | |
paul@15 | 525 | Allow the channel to receive events when disabled: |
paul@15 | 526 | DCHxCON<6> = CHAED = 1 |
paul@15 | 527 | */ |
paul@15 | 528 | |
paul@15 | 529 | la $v0, DCH1CON |
paul@15 | 530 | li $v1, 0b1100011 |
paul@15 | 531 | sw $v1, 0($v0) |
paul@15 | 532 | |
paul@59 | 533 | la $v0, DCH2CON |
paul@59 | 534 | li $v1, 0b1100011 |
paul@59 | 535 | sw $v1, 0($v0) |
paul@59 | 536 | |
paul@15 | 537 | /* |
paul@5 | 538 | Initiate channel transfers when the initiating interrupt condition |
paul@5 | 539 | occurs: |
paul@9 | 540 | DCHxECON<15:8> = CHSIRQ<7:0> = timer 2 interrupt |
paul@11 | 541 | DCHxECON<4> = SIRQEN = 1 |
paul@20 | 542 | |
paul@20 | 543 | For now, however, prevent initiation by not setting SIRQEN. |
paul@5 | 544 | */ |
paul@3 | 545 | |
paul@3 | 546 | la $v0, DCH0ECON |
paul@20 | 547 | li $v1, (9 << 8) |
paul@3 | 548 | sw $v1, 0($v0) |
paul@1 | 549 | |
paul@3 | 550 | /* |
paul@60 | 551 | Initiate line channel transfer when channel 0 is finished: |
paul@60 | 552 | Initiate reset channel transfer when channel 1 is finished: |
paul@60 | 553 | DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 or 1 interrupt |
paul@15 | 554 | DCHxECON<4> = SIRQEN = 1 |
paul@15 | 555 | */ |
paul@15 | 556 | |
paul@15 | 557 | la $v0, DCH1ECON |
paul@15 | 558 | li $v1, (60 << 8) | (1 << 4) |
paul@15 | 559 | sw $v1, 0($v0) |
paul@15 | 560 | |
paul@59 | 561 | la $v0, DCH2ECON |
paul@59 | 562 | li $v1, (61 << 8) | (1 << 4) |
paul@59 | 563 | sw $v1, 0($v0) |
paul@59 | 564 | |
paul@15 | 565 | /* |
paul@15 | 566 | The line channel has a cell size of the number bytes in a line: |
paul@9 | 567 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH |
paul@3 | 568 | */ |
paul@3 | 569 | |
paul@60 | 570 | la $v0, DCH1CSIZ |
paul@9 | 571 | li $v1, LINE_LENGTH |
paul@3 | 572 | sw $v1, 0($v0) |
paul@1 | 573 | |
paul@3 | 574 | /* |
paul@60 | 575 | The start and reset channels have a cell size of a single zero byte: |
paul@49 | 576 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1 |
paul@15 | 577 | */ |
paul@15 | 578 | |
paul@15 | 579 | li $v1, 1 |
paul@60 | 580 | |
paul@60 | 581 | la $v0, DCH0CSIZ |
paul@15 | 582 | sw $v1, 0($v0) |
paul@15 | 583 | |
paul@59 | 584 | la $v0, DCH2CSIZ |
paul@15 | 585 | sw $v1, 0($v0) |
paul@15 | 586 | |
paul@15 | 587 | /* |
paul@11 | 588 | The source has a size identical to the cell size: |
paul@49 | 589 | DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1 |
paul@3 | 590 | */ |
paul@3 | 591 | |
paul@60 | 592 | la $v0, DCH1SSIZ |
paul@9 | 593 | li $v1, LINE_LENGTH |
paul@3 | 594 | sw $v1, 0($v0) |
paul@3 | 595 | |
paul@15 | 596 | li $v1, 1 |
paul@60 | 597 | |
paul@60 | 598 | la $v0, DCH0SSIZ |
paul@15 | 599 | sw $v1, 0($v0) |
paul@15 | 600 | |
paul@59 | 601 | la $v0, DCH2SSIZ |
paul@15 | 602 | sw $v1, 0($v0) |
paul@15 | 603 | |
paul@3 | 604 | /* |
paul@5 | 605 | The source address is the physical address of the line data: |
paul@11 | 606 | DCHxSSA = physical(line data address) |
paul@3 | 607 | */ |
paul@1 | 608 | |
paul@60 | 609 | la $v0, DCH1SSA |
paul@38 | 610 | li $v1, SCREEN_BASE |
paul@38 | 611 | sw $v1, 0($v0) |
paul@3 | 612 | |
paul@3 | 613 | /* |
paul@60 | 614 | For the start and reset channels, a single byte of zero is transferred: |
paul@15 | 615 | DCHxSSA = physical(zero data address) |
paul@15 | 616 | */ |
paul@15 | 617 | |
paul@15 | 618 | la $v1, zerodata |
paul@15 | 619 | li $t8, KSEG0_BASE |
paul@15 | 620 | subu $v1, $v1, $t8 |
paul@60 | 621 | |
paul@60 | 622 | la $v0, DCH0SSA |
paul@59 | 623 | sw $v1, 0($v0) |
paul@59 | 624 | |
paul@59 | 625 | la $v0, DCH2SSA |
paul@15 | 626 | sw $v1, 0($v0) |
paul@15 | 627 | |
paul@15 | 628 | /* |
paul@11 | 629 | The destination has a size of 1 byte: |
paul@3 | 630 | DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1 |
paul@3 | 631 | */ |
paul@3 | 632 | |
paul@71 | 633 | li $v1, 1 |
paul@71 | 634 | |
paul@3 | 635 | la $v0, DCH0DSIZ |
paul@3 | 636 | sw $v1, 0($v0) |
paul@3 | 637 | |
paul@15 | 638 | la $v0, DCH1DSIZ |
paul@15 | 639 | sw $v1, 0($v0) |
paul@15 | 640 | |
paul@59 | 641 | la $v0, DCH2DSIZ |
paul@59 | 642 | sw $v1, 0($v0) |
paul@59 | 643 | |
paul@3 | 644 | /* |
paul@15 | 645 | The destination address is the physical address of PORTB: |
paul@15 | 646 | DCHxDSA = physical(PORTB) |
paul@3 | 647 | */ |
paul@3 | 648 | |
paul@15 | 649 | li $v1, PORTB |
paul@3 | 650 | li $t8, KSEG1_BASE |
paul@3 | 651 | subu $v1, $v1, $t8 |
paul@71 | 652 | |
paul@71 | 653 | la $v0, DCH0DSA |
paul@3 | 654 | sw $v1, 0($v0) |
paul@3 | 655 | |
paul@15 | 656 | la $v0, DCH1DSA |
paul@15 | 657 | sw $v1, 0($v0) |
paul@15 | 658 | |
paul@59 | 659 | la $v0, DCH2DSA |
paul@59 | 660 | sw $v1, 0($v0) |
paul@59 | 661 | |
paul@7 | 662 | /* |
paul@7 | 663 | Use the block transfer completion interrupt to indicate when the source |
paul@7 | 664 | address can be updated. |
paul@7 | 665 | */ |
paul@7 | 666 | |
paul@3 | 667 | la $v0, DCH0INT |
paul@7 | 668 | li $v1, (1 << 19) /* CHBCIE = 1 */ |
paul@7 | 669 | sw $v1, 0($v0) |
paul@7 | 670 | |
paul@59 | 671 | la $v0, DCH1INT |
paul@59 | 672 | li $v1, (1 << 19) /* CHBCIE = 1 */ |
paul@59 | 673 | sw $v1, 0($v0) |
paul@59 | 674 | |
paul@7 | 675 | /* Enable interrupt for address updating. */ |
paul@7 | 676 | |
paul@7 | 677 | la $v0, IPC10 |
paul@59 | 678 | li $v1, 0b1111100011111 /* DMA1IP, DMA1IS, DMA0IP, DMA0IS = 0 */ |
paul@7 | 679 | sw $v1, CLR($v0) |
paul@59 | 680 | li $v1, 0b1111100011111 /* DMA1IP, DMA0IP = 7, DMA1IS, DMA0IS = 3 */ |
paul@7 | 681 | sw $v1, SET($v0) |
paul@7 | 682 | |
paul@7 | 683 | la $v0, IEC1 |
paul@59 | 684 | li $v1, (0b11 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 1 */ |
paul@9 | 685 | sw $v1, SET($v0) |
paul@1 | 686 | |
paul@60 | 687 | /* Enable start channel. */ |
paul@3 | 688 | |
paul@3 | 689 | la $v0, DCH0CON |
paul@3 | 690 | li $v1, 0b10000000 |
paul@3 | 691 | sw $v1, SET($v0) |
paul@3 | 692 | |
paul@1 | 693 | jr $ra |
paul@1 | 694 | nop |
paul@1 | 695 | |
paul@15 | 696 | zerodata: |
paul@15 | 697 | .word 0 |
paul@15 | 698 | |
paul@1 | 699 | |
paul@1 | 700 | |
paul@77 | 701 | /* UART initialisation. */ |
paul@77 | 702 | |
paul@77 | 703 | init_uart: |
paul@77 | 704 | /* Initialise UART. */ |
paul@77 | 705 | |
paul@77 | 706 | la $v0, U1BRG |
paul@77 | 707 | li $v1, 12 /* U1BRG<15:0> = BRG = (FPB / (16 * baudrate)) - 1 = (24000000 / (16 * 115200)) - 1 = 12 */ |
paul@77 | 708 | sw $v1, 0($v0) |
paul@77 | 709 | |
paul@77 | 710 | la $v0, U1MODE |
paul@77 | 711 | li $v1, (1 << 15) /* U1MODE<15> = ON = 0 */ |
paul@77 | 712 | sw $v1, CLR($v0) |
paul@77 | 713 | |
paul@77 | 714 | /* Start UART. */ |
paul@77 | 715 | |
paul@77 | 716 | la $v0, U1STA |
paul@77 | 717 | li $v1, (1 << 10) /* U1STA<10> = UTXEN = 1 */ |
paul@77 | 718 | sw $v1, SET($v0) |
paul@77 | 719 | |
paul@77 | 720 | la $v0, U1MODE |
paul@77 | 721 | li $v1, (1 << 15) /* U1MODE<15> = ON = 1 */ |
paul@77 | 722 | sw $v1, SET($v0) |
paul@77 | 723 | |
paul@77 | 724 | jr $ra |
paul@77 | 725 | nop |
paul@77 | 726 | |
paul@77 | 727 | |
paul@77 | 728 | |
paul@9 | 729 | /* Utilities. */ |
paul@9 | 730 | |
paul@9 | 731 | handle_error_level: |
paul@9 | 732 | mfc0 $t3, CP0_STATUS |
paul@9 | 733 | li $t4, ~(STATUS_ERL | STATUS_EXL) |
paul@9 | 734 | and $t3, $t3, $t4 |
paul@9 | 735 | mtc0 $t3, CP0_STATUS |
paul@9 | 736 | jr $ra |
paul@9 | 737 | nop |
paul@9 | 738 | |
paul@9 | 739 | enable_interrupts: |
paul@9 | 740 | mfc0 $t3, CP0_STATUS |
paul@9 | 741 | li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */ |
paul@9 | 742 | and $t3, $t3, $t4 |
paul@69 | 743 | ori $t3, $t3, (3 << STATUS_IRQ_SHIFT) |
paul@9 | 744 | li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */ |
paul@9 | 745 | and $t3, $t3, $t4 |
paul@9 | 746 | ori $t3, $t3, STATUS_IE |
paul@9 | 747 | mtc0 $t3, CP0_STATUS |
paul@9 | 748 | jr $ra |
paul@9 | 749 | nop |
paul@9 | 750 | |
paul@9 | 751 | init_interrupts: |
paul@9 | 752 | mfc0 $t3, CP0_DEBUG |
paul@9 | 753 | li $t4, ~DEBUG_DM |
paul@9 | 754 | and $t3, $t3, $t4 |
paul@9 | 755 | mtc0 $t3, CP0_DEBUG |
paul@9 | 756 | |
paul@9 | 757 | mfc0 $t3, CP0_STATUS |
paul@11 | 758 | li $t4, STATUS_BEV /* BEV = 1 or EBASE cannot be set */ |
paul@9 | 759 | or $t3, $t3, $t4 |
paul@9 | 760 | mtc0 $t3, CP0_STATUS |
paul@9 | 761 | |
paul@9 | 762 | la $t3, exception_handler |
paul@9 | 763 | mtc0 $t3, CP0_EBASE /* EBASE = exception_handler */ |
paul@9 | 764 | |
paul@9 | 765 | li $t3, 0x20 /* Must be non-zero or the CPU gets upset */ |
paul@9 | 766 | mtc0 $t3, CP0_INTCTL |
paul@9 | 767 | |
paul@9 | 768 | li $t3, CAUSE_IV /* IV = 1 (use EBASE+0x200 for interrupts) */ |
paul@9 | 769 | mtc0 $t3, CP0_CAUSE |
paul@9 | 770 | |
paul@9 | 771 | jr $ra |
paul@9 | 772 | nop |
paul@9 | 773 | |
paul@9 | 774 | |
paul@9 | 775 | |
paul@9 | 776 | /* Exception servicing. */ |
paul@9 | 777 | |
paul@9 | 778 | .section .flash, "a" |
paul@9 | 779 | |
paul@33 | 780 | /* TLB error servicing. */ |
paul@33 | 781 | |
paul@33 | 782 | tlb_handler: |
paul@9 | 783 | j exception_handler |
paul@9 | 784 | nop |
paul@9 | 785 | |
paul@9 | 786 | |
paul@9 | 787 | |
paul@33 | 788 | /* General exception servicing. */ |
paul@33 | 789 | |
paul@33 | 790 | .org 0x180 |
paul@33 | 791 | |
paul@33 | 792 | exception_handler: |
paul@33 | 793 | j exc_handler |
paul@33 | 794 | nop |
paul@33 | 795 | |
paul@33 | 796 | |
paul@45 | 797 | |
paul@9 | 798 | /* Interrupt servicing. */ |
paul@9 | 799 | |
paul@9 | 800 | .org 0x200 |
paul@9 | 801 | |
paul@9 | 802 | interrupt_handler: |
paul@9 | 803 | |
paul@78 | 804 | /* |
paul@78 | 805 | Save affected registers, restoring IRQ state and switching to the IRQ |
paul@78 | 806 | stack. |
paul@78 | 807 | */ |
paul@38 | 808 | |
paul@38 | 809 | li $k0, IRQ_STACK_LIMIT |
paul@78 | 810 | save_affected |
paul@78 | 811 | load_state |
paul@38 | 812 | li $sp, IRQ_STACK_TOP |
paul@38 | 813 | |
paul@47 | 814 | /* |
paul@48 | 815 | The timer interrupt will only occur outside the visible region, but the |
paul@48 | 816 | interrupt condition will still occur as the timer wraps around. |
paul@75 | 817 | |
paul@75 | 818 | Here, we deliberately ignore the timer condition during the visible/ |
paul@75 | 819 | active region. |
paul@75 | 820 | |
paul@75 | 821 | The DMA interrupt should only be active within the visible region. |
paul@47 | 822 | */ |
paul@47 | 823 | |
paul@47 | 824 | la $t8, visible_active |
paul@47 | 825 | beq $s1, $t8, irq_dma |
paul@47 | 826 | nop |
paul@47 | 827 | |
paul@75 | 828 | /* Check for a timer interrupt condition. */ |
paul@9 | 829 | |
paul@75 | 830 | la $v0, IFS0 |
paul@75 | 831 | lw $v1, 0($v0) |
paul@75 | 832 | andi $v1, $v1, (1 << 9) /* T2IF */ |
paul@75 | 833 | beqz $v1, irq_exit |
paul@75 | 834 | nop |
paul@9 | 835 | |
paul@75 | 836 | j irq_handle |
paul@9 | 837 | nop |
paul@9 | 838 | |
paul@9 | 839 | irq_dma: |
paul@9 | 840 | /* Check for a DMA interrupt condition. */ |
paul@9 | 841 | |
paul@9 | 842 | la $v0, IFS1 |
paul@9 | 843 | lw $v1, 0($v0) |
paul@59 | 844 | li $t8, (0b11 << 28) /* DMA1IF, DMA0IF */ |
paul@9 | 845 | and $v1, $v1, $t8 |
paul@9 | 846 | beqz $v1, irq_exit |
paul@9 | 847 | nop |
paul@9 | 848 | |
paul@44 | 849 | /* Clear the DMA interrupt condition. */ |
paul@44 | 850 | |
paul@44 | 851 | sw $v1, CLR($v0) |
paul@44 | 852 | |
paul@9 | 853 | /* Test the block transfer completion interrupt flag. */ |
paul@9 | 854 | |
paul@9 | 855 | la $v0, DCH0INT |
paul@9 | 856 | lw $v1, 0($v0) |
paul@9 | 857 | andi $v1, $v1, (1 << 3) /* CHBCIF */ |
paul@59 | 858 | beqz $v1, irq_dma_next |
paul@59 | 859 | nop |
paul@59 | 860 | |
paul@83 | 861 | j irq_handle |
paul@83 | 862 | nop |
paul@59 | 863 | |
paul@59 | 864 | irq_dma_next: |
paul@59 | 865 | /* Test the block transfer completion interrupt flag. */ |
paul@59 | 866 | |
paul@59 | 867 | la $v0, DCH1INT |
paul@59 | 868 | lw $v1, 0($v0) |
paul@59 | 869 | andi $v1, $v1, (1 << 3) /* CHBCIF */ |
paul@44 | 870 | beqz $v1, irq_exit |
paul@9 | 871 | nop |
paul@9 | 872 | |
paul@75 | 873 | irq_handle: |
paul@75 | 874 | /* Clear the interrupt condition. */ |
paul@9 | 875 | |
paul@9 | 876 | sw $v1, CLR($v0) |
paul@9 | 877 | |
paul@75 | 878 | /* Increment the line counter. */ |
paul@47 | 879 | |
paul@47 | 880 | addiu $s0, $s0, 1 |
paul@47 | 881 | |
paul@75 | 882 | /* Jump to the event handler. */ |
paul@47 | 883 | |
paul@47 | 884 | jalr $s1 |
paul@47 | 885 | nop |
paul@47 | 886 | |
paul@9 | 887 | irq_exit: |
paul@78 | 888 | /* |
paul@78 | 889 | Save IRQ state and restore the affected registers, switching back to the |
paul@78 | 890 | original stack. |
paul@78 | 891 | */ |
paul@38 | 892 | |
paul@38 | 893 | li $k0, IRQ_STACK_LIMIT |
paul@78 | 894 | save_state |
paul@78 | 895 | load_affected |
paul@38 | 896 | |
paul@9 | 897 | eret |
paul@9 | 898 | nop |
paul@9 | 899 | |
paul@9 | 900 | |
paul@9 | 901 | |
paul@9 | 902 | /* Event routines. */ |
paul@9 | 903 | |
paul@9 | 904 | /* The vertical back porch. */ |
paul@9 | 905 | |
paul@9 | 906 | vbp_active: |
paul@9 | 907 | /* Test for visible region. */ |
paul@9 | 908 | |
paul@9 | 909 | sltiu $v0, $s0, VISIBLE_START |
paul@9 | 910 | bnez $v0, _vbp_active_ret |
paul@9 | 911 | nop |
paul@9 | 912 | |
paul@9 | 913 | /* Start the visible region. */ |
paul@9 | 914 | |
paul@9 | 915 | la $s1, visible_active |
paul@9 | 916 | |
paul@17 | 917 | /* Reset the line address. */ |
paul@17 | 918 | |
paul@17 | 919 | move $s2, $s3 |
paul@17 | 920 | |
paul@43 | 921 | /* Update the source address. */ |
paul@43 | 922 | |
paul@60 | 923 | la $v0, DCH1SSA |
paul@43 | 924 | sw $s2, 0($v0) |
paul@43 | 925 | |
paul@69 | 926 | /* |
paul@69 | 927 | Suspend delivery of the timer interrupt during the visible period. |
paul@69 | 928 | The condition still occurs, however. |
paul@69 | 929 | */ |
paul@47 | 930 | |
paul@69 | 931 | la $v0, IPC2 |
paul@76 | 932 | lw $v1, 0($v0) |
paul@76 | 933 | li $t8, ~0b11111 |
paul@76 | 934 | and $v1, $v1, $t8 /* T2IP = 0; T2IS = 0 */ |
paul@76 | 935 | ori $v1, $v1, 0b00111 /* T2IP = 1; T2IS = 3 */ |
paul@76 | 936 | sw $v1, 0($v0) |
paul@69 | 937 | |
paul@74 | 938 | /* Enable the start channel for timer event transfer initiation. */ |
paul@71 | 939 | |
paul@71 | 940 | la $v0, DCH0ECON |
paul@71 | 941 | li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */ |
paul@71 | 942 | sw $v1, SET($v0) |
paul@71 | 943 | |
paul@9 | 944 | _vbp_active_ret: |
paul@9 | 945 | jr $ra |
paul@9 | 946 | nop |
paul@9 | 947 | |
paul@9 | 948 | |
paul@9 | 949 | |
paul@9 | 950 | /* The visible region. */ |
paul@9 | 951 | |
paul@9 | 952 | visible_active: |
paul@9 | 953 | /* Test for front porch. */ |
paul@9 | 954 | |
paul@9 | 955 | sltiu $v0, $s0, VFP_START |
paul@75 | 956 | bnez $v0, visible_update_address |
paul@9 | 957 | nop |
paul@9 | 958 | |
paul@9 | 959 | /* Start the front porch region. */ |
paul@9 | 960 | |
paul@9 | 961 | la $s1, vfp_active |
paul@9 | 962 | |
paul@69 | 963 | /* Restore delivery of the timer interrupt after the visible period. */ |
paul@69 | 964 | |
paul@69 | 965 | la $v0, IPC2 |
paul@76 | 966 | lw $v1, 0($v0) |
paul@76 | 967 | li $t8, ~0b11111 |
paul@76 | 968 | and $v1, $v1, $t8 /* T2IP = 0; T2IS = 0 */ |
paul@76 | 969 | ori $v1, $v1, 0b11111 /* T2IP = 7; T2IS = 3 */ |
paul@76 | 970 | sw $v1, 0($v0) |
paul@47 | 971 | |
paul@83 | 972 | /* Disable the start channel. */ |
paul@75 | 973 | |
paul@75 | 974 | la $v0, DCH0ECON |
paul@75 | 975 | li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */ |
paul@75 | 976 | sw $v1, CLR($v0) |
paul@75 | 977 | |
paul@9 | 978 | _visible_active_ret: |
paul@9 | 979 | jr $ra |
paul@9 | 980 | nop |
paul@9 | 981 | |
paul@9 | 982 | |
paul@9 | 983 | |
paul@45 | 984 | /* DMA update routine. */ |
paul@45 | 985 | |
paul@45 | 986 | visible_update_address: |
paul@45 | 987 | |
paul@45 | 988 | /* |
paul@45 | 989 | Update the line data address if the line counter (referring to the |
paul@45 | 990 | next line) is even. |
paul@45 | 991 | */ |
paul@45 | 992 | |
paul@45 | 993 | andi $t8, $s0, 1 |
paul@45 | 994 | bnez $t8, _visible_update_ret |
paul@45 | 995 | nop |
paul@45 | 996 | |
paul@45 | 997 | /* Reference the next line and update the DMA source address. */ |
paul@45 | 998 | |
paul@45 | 999 | addiu $s2, $s2, LINE_LENGTH |
paul@45 | 1000 | |
paul@45 | 1001 | /* Test for wraparound. */ |
paul@45 | 1002 | |
paul@45 | 1003 | li $t8, (SCREEN_BASE + SCREEN_SIZE) |
paul@45 | 1004 | sltu $t8, $s2, $t8 |
paul@45 | 1005 | bnez $t8, _visible_dma_update |
paul@45 | 1006 | nop |
paul@45 | 1007 | |
paul@45 | 1008 | /* Reset the source address. */ |
paul@45 | 1009 | |
paul@45 | 1010 | li $s2, SCREEN_BASE |
paul@45 | 1011 | |
paul@45 | 1012 | _visible_dma_update: |
paul@45 | 1013 | |
paul@45 | 1014 | /* Update the source address. */ |
paul@45 | 1015 | |
paul@60 | 1016 | la $v0, DCH1SSA |
paul@45 | 1017 | sw $s2, 0($v0) |
paul@45 | 1018 | |
paul@45 | 1019 | _visible_update_ret: |
paul@75 | 1020 | jr $ra |
paul@45 | 1021 | nop |
paul@45 | 1022 | |
paul@45 | 1023 | |
paul@45 | 1024 | |
paul@9 | 1025 | /* Within the vertical front porch. */ |
paul@9 | 1026 | |
paul@9 | 1027 | vfp_active: |
paul@9 | 1028 | /* Test for vsync. */ |
paul@9 | 1029 | |
paul@9 | 1030 | sltiu $v0, $s0, VSYNC_START |
paul@9 | 1031 | bnez $v0, _vfp_active_ret |
paul@9 | 1032 | nop |
paul@9 | 1033 | |
paul@9 | 1034 | /* Start the vsync. */ |
paul@9 | 1035 | |
paul@9 | 1036 | la $s1, vsync_active |
paul@9 | 1037 | |
paul@9 | 1038 | /* Bring vsync low when the next line starts. */ |
paul@9 | 1039 | |
paul@9 | 1040 | la $v0, OC2CON |
paul@9 | 1041 | li $v1, 0b010 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@9 | 1042 | sw $v1, 0($v0) |
paul@9 | 1043 | |
paul@9 | 1044 | _vfp_active_ret: |
paul@9 | 1045 | jr $ra |
paul@9 | 1046 | nop |
paul@9 | 1047 | |
paul@9 | 1048 | |
paul@9 | 1049 | |
paul@9 | 1050 | /* The vsync period. */ |
paul@9 | 1051 | |
paul@9 | 1052 | vsync_active: |
paul@9 | 1053 | /* Test for front porch. */ |
paul@9 | 1054 | |
paul@9 | 1055 | sltiu $v0, $s0, VSYNC_END |
paul@9 | 1056 | bnez $v0, _vsync_active_ret |
paul@9 | 1057 | nop |
paul@9 | 1058 | |
paul@9 | 1059 | /* Start the back porch. */ |
paul@9 | 1060 | |
paul@9 | 1061 | move $s0, $zero |
paul@9 | 1062 | la $s1, vbp_active |
paul@9 | 1063 | |
paul@9 | 1064 | /* Bring vsync high when the next line starts. */ |
paul@9 | 1065 | |
paul@9 | 1066 | la $v0, OC2CON |
paul@9 | 1067 | li $v1, 0b001 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 001 (single compare, output driven high) */ |
paul@9 | 1068 | sw $v1, 0($v0) |
paul@9 | 1069 | |
paul@9 | 1070 | _vsync_active_ret: |
paul@9 | 1071 | jr $ra |
paul@9 | 1072 | nop |
paul@79 | 1073 | |
paul@79 | 1074 | |
paul@79 | 1075 | |
paul@79 | 1076 | /* Exception handler. */ |
paul@79 | 1077 | |
paul@79 | 1078 | exc_handler: |
paul@79 | 1079 | mfc0 $t7, CP0_ERROREPC |
paul@79 | 1080 | nop |
paul@79 | 1081 | |
paul@79 | 1082 | exc_write_word: |
paul@79 | 1083 | li $t8, 32 |
paul@79 | 1084 | la $v0, U1TXREG |
paul@79 | 1085 | exc_loop: |
paul@79 | 1086 | addiu $t8, $t8, -4 |
paul@79 | 1087 | srlv $v1, $t7, $t8 /* $v1 = $t7 >> $t8 */ |
paul@79 | 1088 | andi $v1, $v1, 0xF |
paul@79 | 1089 | addiu $t9, $v1, -10 /* $t9 >= 10? */ |
paul@79 | 1090 | bgez $t9, exc_alpha |
paul@79 | 1091 | nop |
paul@79 | 1092 | exc_digit: |
paul@79 | 1093 | addiu $v1, $v1, 48 /* convert to digit: '0' */ |
paul@79 | 1094 | j exc_write |
paul@79 | 1095 | nop |
paul@79 | 1096 | exc_alpha: |
paul@79 | 1097 | addiu $v1, $v1, 55 /* convert to alpha: 'A' - 10 */ |
paul@79 | 1098 | exc_write: |
paul@79 | 1099 | sw $v1, 0($v0) |
paul@79 | 1100 | bnez $t8, exc_loop |
paul@79 | 1101 | nop |
paul@79 | 1102 | exc_loop_end: |
paul@79 | 1103 | li $v1, '\n' |
paul@79 | 1104 | sw $v1, 0($v0) |
paul@79 | 1105 | |
paul@79 | 1106 | exc_handler_end: |
paul@79 | 1107 | j exc_handler_end |
paul@79 | 1108 | nop |