paul@0 | 1 | /* |
paul@0 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@0 | 22 | |
paul@9 | 23 | #define LINE_LENGTH 160 /* pixels */ |
paul@9 | 24 | |
paul@16 | 25 | #define HFREQ_LIMIT 936 /* 30MHz cycles */ |
paul@16 | 26 | #define HSYNC_START 800 /* 30MHz cycles */ |
paul@16 | 27 | #define HSYNC_LIMIT 112 /* 30MHz cycles */ |
paul@9 | 28 | #define HSYNC_END (HSYNC_START + HSYNC_LIMIT) |
paul@9 | 29 | |
paul@9 | 30 | #define VISIBLE_START 15 /* horizontal lines, back porch end */ |
paul@9 | 31 | #define VFP_START 527 /* horizontal lines, front porch start */ |
paul@9 | 32 | #define VSYNC_START 529 /* horizontal lines, front porch end */ |
paul@9 | 33 | #define VSYNC_END 531 /* horizontal lines, back porch start */ |
paul@9 | 34 | |
paul@9 | 35 | #define SCREEN_SIZE (40 * 1024) |
paul@0 | 36 | |
paul@0 | 37 | /* Disable JTAG functionality on pins. */ |
paul@0 | 38 | |
paul@0 | 39 | .section .devcfg0, "a" |
paul@0 | 40 | .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ |
paul@0 | 41 | |
paul@0 | 42 | /* |
paul@0 | 43 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
paul@9 | 44 | divided by 1, and FRCDIV+PLL selected. |
paul@9 | 45 | |
paul@9 | 46 | The system clock and peripheral clock are therefore the same. |
paul@0 | 47 | |
paul@0 | 48 | The watchdog timer (FWDTEN) is also disabled. |
paul@9 | 49 | |
paul@9 | 50 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
paul@9 | 51 | RPB4. |
paul@0 | 52 | */ |
paul@0 | 53 | |
paul@0 | 54 | .section .devcfg1, "a" |
paul@12 | 55 | .word 0xff7fcfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 0; |
paul@9 | 56 | DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ |
paul@0 | 57 | |
paul@0 | 58 | /* |
paul@0 | 59 | Set the FRC oscillator PLL function with an input division of 4, an output |
paul@16 | 60 | division of 2, a multiplication of 15, yielding a multiplication of 1.875. |
paul@9 | 61 | |
paul@16 | 62 | The FRC is apparently at 16MHz and this produces a system clock of 30MHz. |
paul@0 | 63 | */ |
paul@0 | 64 | |
paul@0 | 65 | .section .devcfg2, "a" |
paul@16 | 66 | .word 0xfff9ff8b /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; |
paul@16 | 67 | DEVCFG2<6:4> = FPLLMUL<2:0> = 000; |
paul@9 | 68 | DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ |
paul@0 | 69 | |
paul@0 | 70 | .text |
paul@0 | 71 | .globl _start |
paul@0 | 72 | |
paul@0 | 73 | _start: |
paul@0 | 74 | /* |
paul@0 | 75 | Configure RAM. |
paul@0 | 76 | See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization |
paul@0 | 77 | */ |
paul@0 | 78 | |
paul@0 | 79 | la $v0, BMXCON |
paul@10 | 80 | lw $v1, 0($v0) |
paul@10 | 81 | li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */ |
paul@10 | 82 | and $v1, $v1, $t8 |
paul@10 | 83 | li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */ |
paul@10 | 84 | ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */ |
paul@10 | 85 | and $v1, $v1, $t8 |
paul@10 | 86 | sw $v1, 0($v0) |
paul@0 | 87 | |
paul@0 | 88 | /* Enable caching. */ |
paul@0 | 89 | |
paul@14 | 90 | mfc0 $v1, CP0_CONFIG |
paul@14 | 91 | li $t8, ~CONFIG_K0 |
paul@14 | 92 | and $v1, $v1, $t8 |
paul@14 | 93 | ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT |
paul@14 | 94 | mtc0 $v1, CP0_CONFIG |
paul@0 | 95 | nop |
paul@0 | 96 | |
paul@0 | 97 | /* Get the RAM size. */ |
paul@0 | 98 | |
paul@3 | 99 | la $v0, BMXDRMSZ |
paul@0 | 100 | lw $v0, 0($v0) |
paul@0 | 101 | |
paul@0 | 102 | /* Initialise the stack pointer. */ |
paul@0 | 103 | |
paul@3 | 104 | li $v1, KSEG0_BASE |
paul@3 | 105 | addu $sp, $v0, $v1 /* sp = KSEG0_BASE + RAM size */ |
paul@0 | 106 | |
paul@9 | 107 | /* Initialise framebuffer. */ |
paul@9 | 108 | |
paul@9 | 109 | jal init_framebuffer |
paul@9 | 110 | nop |
paul@9 | 111 | |
paul@0 | 112 | /* Initialise the globals pointer. */ |
paul@0 | 113 | |
paul@0 | 114 | lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 115 | ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 116 | |
paul@5 | 117 | /* Set pins for output. */ |
paul@0 | 118 | |
paul@0 | 119 | jal init_pins |
paul@0 | 120 | nop |
paul@0 | 121 | |
paul@15 | 122 | la $t0, PORTA |
paul@15 | 123 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@15 | 124 | sw $t1, CLR($t0) |
paul@15 | 125 | |
paul@5 | 126 | jal init_oc_pins |
paul@5 | 127 | nop |
paul@5 | 128 | |
paul@0 | 129 | /* Initialise the status register. */ |
paul@0 | 130 | |
paul@0 | 131 | jal init_interrupts |
paul@0 | 132 | nop |
paul@0 | 133 | |
paul@0 | 134 | /* Initialise timer. */ |
paul@0 | 135 | |
paul@4 | 136 | jal init_timer2 |
paul@0 | 137 | nop |
paul@0 | 138 | |
paul@3 | 139 | /* Initialise DMA. */ |
paul@3 | 140 | |
paul@3 | 141 | jal init_dma |
paul@3 | 142 | nop |
paul@3 | 143 | |
paul@15 | 144 | /* Initialise OC1 and OC2. */ |
paul@5 | 145 | |
paul@9 | 146 | jal init_oc |
paul@3 | 147 | nop |
paul@3 | 148 | |
paul@0 | 149 | /* Enable interrupts and loop. */ |
paul@0 | 150 | |
paul@0 | 151 | jal enable_interrupts |
paul@0 | 152 | nop |
paul@0 | 153 | |
paul@0 | 154 | jal handle_error_level |
paul@0 | 155 | nop |
paul@0 | 156 | |
paul@3 | 157 | /* Main program. */ |
paul@3 | 158 | |
paul@9 | 159 | li $a1, 5000000 /* counter = 5000000 */ |
paul@3 | 160 | |
paul@3 | 161 | /* Initialise the display state. */ |
paul@3 | 162 | |
paul@1 | 163 | li $s0, 0 /* line counter */ |
paul@9 | 164 | la $s1, vbp_active /* current event */ |
paul@6 | 165 | move $s2, $zero /* line address */ |
paul@3 | 166 | |
paul@3 | 167 | /* Monitoring loop. */ |
paul@0 | 168 | loop: |
paul@3 | 169 | addiu $a1, $a1, -1 /* counter -= 1 */ |
paul@3 | 170 | bnez $a1, loop /* until counter == 0 */ |
paul@0 | 171 | nop |
paul@0 | 172 | |
paul@9 | 173 | li $a1, 5000000 /* counter = 5000000 */ |
paul@0 | 174 | |
paul@15 | 175 | la $t0, PORTA |
paul@15 | 176 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@3 | 177 | sw $t1, INV($t0) |
paul@0 | 178 | |
paul@0 | 179 | _next: |
paul@0 | 180 | j loop |
paul@0 | 181 | nop |
paul@0 | 182 | |
paul@0 | 183 | |
paul@0 | 184 | |
paul@0 | 185 | init_pins: |
paul@1 | 186 | /* DEVCFG0<2> needs setting to 0 before the program is run. */ |
paul@0 | 187 | |
paul@3 | 188 | la $v0, CFGCON |
paul@0 | 189 | li $v1, (1 << 3) /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 190 | sw $v1, CLR($v0) |
paul@0 | 191 | |
paul@3 | 192 | init_outputs: |
paul@3 | 193 | /* Remove analogue features from pins. */ |
paul@3 | 194 | |
paul@3 | 195 | la $v0, ANSELA |
paul@3 | 196 | sw $zero, 0($v0) /* ANSELA = 0 */ |
paul@3 | 197 | la $v0, ANSELB |
paul@3 | 198 | sw $zero, 0($v0) /* ANSELB = 0 */ |
paul@3 | 199 | |
paul@3 | 200 | la $v0, TRISA |
paul@3 | 201 | sw $zero, 0($v0) |
paul@0 | 202 | la $v0, TRISB |
paul@3 | 203 | sw $zero, 0($v0) |
paul@3 | 204 | |
paul@9 | 205 | la $v0, PORTA |
paul@9 | 206 | sw $zero, 0($v0) |
paul@9 | 207 | la $v0, PORTB |
paul@9 | 208 | sw $zero, 0($v0) |
paul@0 | 209 | |
paul@3 | 210 | jr $ra |
paul@0 | 211 | nop |
paul@0 | 212 | |
paul@0 | 213 | |
paul@0 | 214 | |
paul@0 | 215 | /* Initialisation routines. */ |
paul@0 | 216 | |
paul@4 | 217 | init_timer2: |
paul@0 | 218 | |
paul@4 | 219 | /* Initialise Timer2 interrupt. */ |
paul@0 | 220 | |
paul@4 | 221 | la $v0, T2CON |
paul@4 | 222 | sw $zero, 0($v0) /* T2CON = 0 */ |
paul@0 | 223 | nop |
paul@0 | 224 | |
paul@4 | 225 | la $v0, TMR2 |
paul@4 | 226 | sw $zero, 0($v0) /* TMR2 = 0 */ |
paul@5 | 227 | |
paul@4 | 228 | la $v0, PR2 |
paul@0 | 229 | li $v1, HFREQ_LIMIT |
paul@4 | 230 | sw $v1, 0($v0) /* PR2 = HFREQ_LIMIT */ |
paul@0 | 231 | |
paul@4 | 232 | /* Initialise Timer2 interrupt. */ |
paul@0 | 233 | |
paul@0 | 234 | la $v0, IFS0 |
paul@4 | 235 | li $v1, (1 << 9) |
paul@5 | 236 | sw $v1, CLR($v0) /* T2IF = 0 */ |
paul@5 | 237 | |
paul@4 | 238 | la $v0, IPC2 |
paul@5 | 239 | li $v1, 0b11111 |
paul@5 | 240 | sw $v1, CLR($v0) /* T2IP, T2IS = 0 */ |
paul@5 | 241 | |
paul@4 | 242 | la $v0, IPC2 |
paul@5 | 243 | li $v1, 0b11111 |
paul@5 | 244 | sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */ |
paul@5 | 245 | |
paul@0 | 246 | la $v0, IEC0 |
paul@4 | 247 | li $v1, (1 << 9) |
paul@5 | 248 | sw $v1, SET($v0) /* T2IE = 1 */ |
paul@0 | 249 | |
paul@0 | 250 | /* Start timer. */ |
paul@0 | 251 | |
paul@4 | 252 | la $v0, T2CON |
paul@5 | 253 | li $v1, (1 << 15) |
paul@5 | 254 | sw $v1, SET($v0) /* ON = 1 */ |
paul@5 | 255 | |
paul@5 | 256 | jr $ra |
paul@5 | 257 | nop |
paul@5 | 258 | |
paul@5 | 259 | |
paul@5 | 260 | |
paul@5 | 261 | /* |
paul@5 | 262 | Output compare initialisation. |
paul@5 | 263 | |
paul@15 | 264 | Timer2 will be used to trigger two events using OC1: one initiating the hsync |
paul@9 | 265 | pulse, and one terminating the pulse. The pulse should appear after the line |
paul@9 | 266 | data has been transferred using DMA, but this is achieved by just choosing |
paul@9 | 267 | suitable start and end values. |
paul@5 | 268 | |
paul@9 | 269 | Using OC2, Timer 2 triggers a level shifting event and OC2 is reconfigured to |
paul@9 | 270 | reverse the level at a later point. |
paul@5 | 271 | */ |
paul@5 | 272 | |
paul@9 | 273 | init_oc: |
paul@15 | 274 | /* Disable OC1 interrupts. */ |
paul@9 | 275 | |
paul@9 | 276 | la $v0, IEC0 |
paul@15 | 277 | li $v1, (1 << 7) /* IEC0<7> = OC1IE = 0 */ |
paul@9 | 278 | sw $v1, CLR($v0) |
paul@9 | 279 | |
paul@9 | 280 | la $v0, IFS0 |
paul@15 | 281 | li $v1, (1 << 7) /* IFS0<7> = OC1IF = 0 */ |
paul@9 | 282 | sw $v1, CLR($v0) |
paul@9 | 283 | |
paul@15 | 284 | /* Initialise OC1. */ |
paul@9 | 285 | |
paul@15 | 286 | la $v0, OC1CON |
paul@15 | 287 | li $v1, 0b101 /* OC1CON<2:0> = OCM<2:0> = 101 (dual compare, continuous pulse) */ |
paul@9 | 288 | sw $v1, 0($v0) |
paul@9 | 289 | |
paul@9 | 290 | /* Pulse start and end. */ |
paul@9 | 291 | |
paul@15 | 292 | la $v0, OC1R |
paul@9 | 293 | li $v1, HSYNC_END /* HSYNC_START for positive polarity */ |
paul@9 | 294 | sw $v1, 0($v0) |
paul@9 | 295 | |
paul@15 | 296 | la $v0, OC1RS |
paul@9 | 297 | li $v1, HSYNC_START /* HSYNC_END for positive polarity */ |
paul@9 | 298 | sw $v1, 0($v0) |
paul@9 | 299 | |
paul@15 | 300 | /* OC1 is enabled. */ |
paul@9 | 301 | |
paul@15 | 302 | la $v0, OC1CON |
paul@9 | 303 | li $v1, (1 << 15) |
paul@9 | 304 | sw $v1, SET($v0) |
paul@9 | 305 | |
paul@9 | 306 | /* Disable OC2 interrupts. */ |
paul@5 | 307 | |
paul@5 | 308 | la $v0, IEC0 |
paul@5 | 309 | li $v1, (1 << 12) /* IEC0<12> = OC2IE = 0 */ |
paul@5 | 310 | sw $v1, CLR($v0) |
paul@5 | 311 | |
paul@5 | 312 | la $v0, IFS0 |
paul@5 | 313 | li $v1, (1 << 12) /* IFS0<12> = OC2IF = 0 */ |
paul@5 | 314 | sw $v1, CLR($v0) |
paul@5 | 315 | |
paul@5 | 316 | /* Initialise OC2. */ |
paul@5 | 317 | |
paul@5 | 318 | la $v0, OC2CON |
paul@9 | 319 | li $v1, 0b010 /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@5 | 320 | sw $v1, 0($v0) |
paul@5 | 321 | |
paul@9 | 322 | /* Set pulse position. */ |
paul@5 | 323 | |
paul@5 | 324 | la $v0, OC2R |
paul@9 | 325 | sw $zero, 0($v0) |
paul@5 | 326 | |
paul@9 | 327 | /* Enable OC2 later. */ |
paul@5 | 328 | |
paul@5 | 329 | jr $ra |
paul@5 | 330 | nop |
paul@5 | 331 | |
paul@5 | 332 | |
paul@5 | 333 | init_oc_pins: |
paul@5 | 334 | /* Unlock the configuration register bits. */ |
paul@5 | 335 | |
paul@5 | 336 | la $v0, SYSKEY |
paul@5 | 337 | sw $zero, 0($v0) |
paul@5 | 338 | li $v1, 0xAA996655 |
paul@5 | 339 | sw $v1, 0($v0) |
paul@5 | 340 | li $v1, 0x556699AA |
paul@5 | 341 | sw $v1, 0($v0) |
paul@5 | 342 | |
paul@5 | 343 | la $v0, CFGCON |
paul@5 | 344 | lw $t8, 0($v0) |
paul@5 | 345 | li $v1, (1 << 13) /* IOLOCK = 0 */ |
paul@5 | 346 | sw $v1, CLR($v0) |
paul@5 | 347 | |
paul@15 | 348 | /* Map OC1 to RPA0. */ |
paul@9 | 349 | |
paul@15 | 350 | la $v0, RPA0R |
paul@15 | 351 | li $v1, 0b0101 /* RPA0R<3:0> = 0101 (OC1) */ |
paul@9 | 352 | sw $v1, 0($v0) |
paul@9 | 353 | |
paul@15 | 354 | /* Map OC2 to RPA1. */ |
paul@5 | 355 | |
paul@15 | 356 | la $v0, RPA1R |
paul@15 | 357 | li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */ |
paul@5 | 358 | sw $v1, 0($v0) |
paul@5 | 359 | |
paul@5 | 360 | la $v0, CFGCON |
paul@5 | 361 | sw $t8, 0($v0) |
paul@5 | 362 | |
paul@5 | 363 | /* Lock the oscillator control register again. */ |
paul@5 | 364 | |
paul@5 | 365 | la $v0, SYSKEY |
paul@5 | 366 | li $v1, 0x33333333 |
paul@5 | 367 | sw $v1, 0($v0) |
paul@0 | 368 | |
paul@0 | 369 | jr $ra |
paul@0 | 370 | nop |
paul@1 | 371 | |
paul@1 | 372 | |
paul@1 | 373 | |
paul@5 | 374 | /* |
paul@5 | 375 | Direct Memory Access initialisation. |
paul@3 | 376 | |
paul@15 | 377 | Write 160 pixels to PORTB for the line data. This is initiated by a timer |
paul@9 | 378 | interrupt. Upon completion of the transfer, a DMA interrupt initiates the |
paul@9 | 379 | address update routine, changing the source address of the DMA channel. |
paul@3 | 380 | */ |
paul@3 | 381 | |
paul@3 | 382 | init_dma: |
paul@3 | 383 | /* Disable DMA interrupts. */ |
paul@1 | 384 | |
paul@3 | 385 | la $v0, IEC1 |
paul@15 | 386 | li $v1, (3 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 0 */ |
paul@3 | 387 | sw $v1, CLR($v0) |
paul@3 | 388 | |
paul@3 | 389 | /* Clear DMA interrupt flags. */ |
paul@1 | 390 | |
paul@3 | 391 | la $v0, IFS1 |
paul@15 | 392 | li $v1, (3 << 28) /* IFS1<29:28> = DMA1IF, DMA0IF = 0 */ |
paul@3 | 393 | sw $v1, CLR($v0) |
paul@3 | 394 | |
paul@3 | 395 | /* Enable DMA. */ |
paul@3 | 396 | |
paul@3 | 397 | la $v0, DMACON |
paul@3 | 398 | li $v1, (1 << 15) |
paul@1 | 399 | sw $v1, SET($v0) |
paul@1 | 400 | |
paul@3 | 401 | /* |
paul@5 | 402 | Initialise a line channel. |
paul@5 | 403 | The line channel will be channel 0 (x = 0). |
paul@3 | 404 | |
paul@3 | 405 | Specify a priority of 3: |
paul@3 | 406 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@3 | 407 | |
paul@15 | 408 | Auto-enable the channel: |
paul@3 | 409 | DCHxCON<4> = CHAEN = 1 |
paul@3 | 410 | */ |
paul@3 | 411 | |
paul@3 | 412 | la $v0, DCH0CON |
paul@3 | 413 | li $v1, 0b10011 |
paul@3 | 414 | sw $v1, 0($v0) |
paul@3 | 415 | |
paul@5 | 416 | /* |
paul@15 | 417 | Initialise a level reset channel. |
paul@15 | 418 | The reset channel will be channel 1 (x = 1). |
paul@15 | 419 | |
paul@15 | 420 | Specify a priority of 3: |
paul@15 | 421 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@15 | 422 | |
paul@15 | 423 | Chain the channel to channel 0: |
paul@15 | 424 | DCHxCON<5> = CHCHN = 1 |
paul@15 | 425 | |
paul@15 | 426 | Allow the channel to receive events when disabled: |
paul@15 | 427 | DCHxCON<6> = CHAED = 1 |
paul@15 | 428 | */ |
paul@15 | 429 | |
paul@15 | 430 | la $v0, DCH1CON |
paul@15 | 431 | li $v1, 0b1100011 |
paul@15 | 432 | sw $v1, 0($v0) |
paul@15 | 433 | |
paul@15 | 434 | /* |
paul@5 | 435 | Initiate channel transfers when the initiating interrupt condition |
paul@5 | 436 | occurs: |
paul@9 | 437 | DCHxECON<15:8> = CHSIRQ<7:0> = timer 2 interrupt |
paul@11 | 438 | DCHxECON<4> = SIRQEN = 1 |
paul@5 | 439 | */ |
paul@3 | 440 | |
paul@3 | 441 | la $v0, DCH0ECON |
paul@9 | 442 | li $v1, (9 << 8) | (1 << 4) |
paul@3 | 443 | sw $v1, 0($v0) |
paul@1 | 444 | |
paul@3 | 445 | /* |
paul@15 | 446 | Initiate reset channel transfer when channel 0 is finished: |
paul@15 | 447 | DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt |
paul@15 | 448 | DCHxECON<4> = SIRQEN = 1 |
paul@15 | 449 | */ |
paul@15 | 450 | |
paul@15 | 451 | la $v0, DCH1ECON |
paul@15 | 452 | li $v1, (60 << 8) | (1 << 4) |
paul@15 | 453 | sw $v1, 0($v0) |
paul@15 | 454 | |
paul@15 | 455 | /* |
paul@15 | 456 | The line channel has a cell size of the number bytes in a line: |
paul@9 | 457 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH |
paul@3 | 458 | */ |
paul@3 | 459 | |
paul@3 | 460 | la $v0, DCH0CSIZ |
paul@9 | 461 | li $v1, LINE_LENGTH |
paul@3 | 462 | sw $v1, 0($v0) |
paul@1 | 463 | |
paul@3 | 464 | /* |
paul@15 | 465 | The reset channel has a cell size of a single zero byte: |
paul@15 | 466 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH |
paul@15 | 467 | */ |
paul@15 | 468 | |
paul@15 | 469 | la $v0, DCH1CSIZ |
paul@15 | 470 | li $v1, 1 |
paul@15 | 471 | sw $v1, 0($v0) |
paul@15 | 472 | |
paul@15 | 473 | /* |
paul@11 | 474 | The source has a size identical to the cell size: |
paul@11 | 475 | DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH |
paul@3 | 476 | */ |
paul@3 | 477 | |
paul@3 | 478 | la $v0, DCH0SSIZ |
paul@9 | 479 | li $v1, LINE_LENGTH |
paul@3 | 480 | sw $v1, 0($v0) |
paul@3 | 481 | |
paul@15 | 482 | la $v0, DCH1SSIZ |
paul@15 | 483 | li $v1, 1 |
paul@15 | 484 | sw $v1, 0($v0) |
paul@15 | 485 | |
paul@3 | 486 | /* |
paul@5 | 487 | The source address is the physical address of the line data: |
paul@11 | 488 | DCHxSSA = physical(line data address) |
paul@3 | 489 | */ |
paul@1 | 490 | |
paul@3 | 491 | la $v0, DCH0SSA |
paul@3 | 492 | sw $zero, 0($v0) |
paul@3 | 493 | |
paul@3 | 494 | /* |
paul@15 | 495 | For the reset channel, a single byte of zero is transferred: |
paul@15 | 496 | DCHxSSA = physical(zero data address) |
paul@15 | 497 | */ |
paul@15 | 498 | |
paul@15 | 499 | la $v0, DCH1SSA |
paul@15 | 500 | la $v1, zerodata |
paul@15 | 501 | li $t8, KSEG0_BASE |
paul@15 | 502 | subu $v1, $v1, $t8 |
paul@15 | 503 | sw $v1, 0($v0) |
paul@15 | 504 | |
paul@15 | 505 | /* |
paul@11 | 506 | The destination has a size of 1 byte: |
paul@3 | 507 | DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1 |
paul@3 | 508 | */ |
paul@3 | 509 | |
paul@3 | 510 | la $v0, DCH0DSIZ |
paul@3 | 511 | li $v1, 1 |
paul@3 | 512 | sw $v1, 0($v0) |
paul@3 | 513 | |
paul@15 | 514 | la $v0, DCH1DSIZ |
paul@15 | 515 | sw $v1, 0($v0) |
paul@15 | 516 | |
paul@3 | 517 | /* |
paul@15 | 518 | The destination address is the physical address of PORTB: |
paul@15 | 519 | DCHxDSA = physical(PORTB) |
paul@3 | 520 | */ |
paul@3 | 521 | |
paul@5 | 522 | la $v0, DCH0DSA |
paul@15 | 523 | li $v1, PORTB |
paul@3 | 524 | li $t8, KSEG1_BASE |
paul@3 | 525 | subu $v1, $v1, $t8 |
paul@3 | 526 | sw $v1, 0($v0) |
paul@3 | 527 | |
paul@15 | 528 | la $v0, DCH1DSA |
paul@15 | 529 | sw $v1, 0($v0) |
paul@15 | 530 | |
paul@7 | 531 | /* |
paul@7 | 532 | Use the block transfer completion interrupt to indicate when the source |
paul@7 | 533 | address can be updated. |
paul@7 | 534 | */ |
paul@7 | 535 | |
paul@3 | 536 | la $v0, DCH0INT |
paul@7 | 537 | li $v1, (1 << 19) /* CHBCIE = 1 */ |
paul@7 | 538 | sw $v1, 0($v0) |
paul@7 | 539 | |
paul@7 | 540 | /* Enable interrupt for address updating. */ |
paul@7 | 541 | |
paul@7 | 542 | la $v0, IPC10 |
paul@7 | 543 | li $v1, 0b11111 /* DMA0IP, DMA0IS = 0 */ |
paul@7 | 544 | sw $v1, CLR($v0) |
paul@7 | 545 | |
paul@7 | 546 | la $v0, IPC10 |
paul@7 | 547 | li $v1, 0b11111 /* DMA0IP = 7, DMA0IS = 3 */ |
paul@7 | 548 | sw $v1, SET($v0) |
paul@7 | 549 | |
paul@7 | 550 | la $v0, IEC1 |
paul@7 | 551 | li $v1, (1 << 28) /* IEC1<28> = DMA0IE = 1 */ |
paul@9 | 552 | sw $v1, SET($v0) |
paul@1 | 553 | |
paul@15 | 554 | /* Enable line channel. */ |
paul@3 | 555 | |
paul@3 | 556 | la $v0, DCH0CON |
paul@3 | 557 | li $v1, 0b10000000 |
paul@3 | 558 | sw $v1, SET($v0) |
paul@3 | 559 | |
paul@1 | 560 | jr $ra |
paul@1 | 561 | nop |
paul@1 | 562 | |
paul@15 | 563 | zerodata: |
paul@15 | 564 | .word 0 |
paul@15 | 565 | |
paul@1 | 566 | |
paul@1 | 567 | |
paul@3 | 568 | /* Framebuffer initialisation. */ |
paul@1 | 569 | |
paul@3 | 570 | init_framebuffer: |
paul@3 | 571 | li $v0, KSEG0_BASE |
paul@9 | 572 | li $t8, SCREEN_SIZE |
paul@9 | 573 | li $v1, 0xff031ce0 |
paul@1 | 574 | |
paul@3 | 575 | _init_fb_loop: |
paul@3 | 576 | sw $v1, 0($v0) |
paul@3 | 577 | addiu $v0, $v0, 4 |
paul@3 | 578 | addiu $t8, $t8, -4 |
paul@3 | 579 | bnez $t8, _init_fb_loop |
paul@1 | 580 | nop |
paul@1 | 581 | |
paul@1 | 582 | jr $ra |
paul@1 | 583 | nop |
paul@9 | 584 | |
paul@9 | 585 | |
paul@9 | 586 | |
paul@9 | 587 | /* Utilities. */ |
paul@9 | 588 | |
paul@9 | 589 | handle_error_level: |
paul@9 | 590 | mfc0 $t3, CP0_STATUS |
paul@9 | 591 | li $t4, ~(STATUS_ERL | STATUS_EXL) |
paul@9 | 592 | and $t3, $t3, $t4 |
paul@9 | 593 | mtc0 $t3, CP0_STATUS |
paul@9 | 594 | jr $ra |
paul@9 | 595 | nop |
paul@9 | 596 | |
paul@9 | 597 | enable_interrupts: |
paul@9 | 598 | mfc0 $t3, CP0_STATUS |
paul@9 | 599 | li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */ |
paul@9 | 600 | and $t3, $t3, $t4 |
paul@9 | 601 | li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */ |
paul@9 | 602 | and $t3, $t3, $t4 |
paul@9 | 603 | ori $t3, $t3, STATUS_IE |
paul@9 | 604 | mtc0 $t3, CP0_STATUS |
paul@9 | 605 | jr $ra |
paul@9 | 606 | nop |
paul@9 | 607 | |
paul@9 | 608 | init_interrupts: |
paul@9 | 609 | mfc0 $t3, CP0_DEBUG |
paul@9 | 610 | li $t4, ~DEBUG_DM |
paul@9 | 611 | and $t3, $t3, $t4 |
paul@9 | 612 | mtc0 $t3, CP0_DEBUG |
paul@9 | 613 | |
paul@9 | 614 | mfc0 $t3, CP0_STATUS |
paul@11 | 615 | li $t4, STATUS_BEV /* BEV = 1 or EBASE cannot be set */ |
paul@9 | 616 | or $t3, $t3, $t4 |
paul@9 | 617 | mtc0 $t3, CP0_STATUS |
paul@9 | 618 | |
paul@9 | 619 | la $t3, exception_handler |
paul@9 | 620 | mtc0 $t3, CP0_EBASE /* EBASE = exception_handler */ |
paul@9 | 621 | |
paul@9 | 622 | li $t3, 0x20 /* Must be non-zero or the CPU gets upset */ |
paul@9 | 623 | mtc0 $t3, CP0_INTCTL |
paul@9 | 624 | |
paul@9 | 625 | li $t3, CAUSE_IV /* IV = 1 (use EBASE+0x200 for interrupts) */ |
paul@9 | 626 | mtc0 $t3, CP0_CAUSE |
paul@9 | 627 | |
paul@9 | 628 | jr $ra |
paul@9 | 629 | nop |
paul@9 | 630 | |
paul@9 | 631 | |
paul@9 | 632 | |
paul@9 | 633 | /* Exception servicing. */ |
paul@9 | 634 | |
paul@9 | 635 | .section .flash, "a" |
paul@9 | 636 | |
paul@9 | 637 | exception_handler: |
paul@9 | 638 | li $t8, 2500000 |
paul@9 | 639 | exc_loop: |
paul@9 | 640 | addiu $t8, $t8, -1 |
paul@9 | 641 | bnez $t8, exc_loop |
paul@9 | 642 | nop |
paul@15 | 643 | la $v0, PORTA |
paul@15 | 644 | li $v1, (1 << 2) /* PORTA<2> = RA2 */ |
paul@9 | 645 | sw $v1, INV($v0) |
paul@9 | 646 | j exception_handler |
paul@9 | 647 | nop |
paul@9 | 648 | |
paul@9 | 649 | |
paul@9 | 650 | |
paul@9 | 651 | /* Interrupt servicing. */ |
paul@9 | 652 | |
paul@9 | 653 | .org 0x200 |
paul@9 | 654 | |
paul@9 | 655 | interrupt_handler: |
paul@9 | 656 | |
paul@9 | 657 | /* Check for a timer interrupt condition. */ |
paul@9 | 658 | |
paul@9 | 659 | la $v0, IFS0 |
paul@9 | 660 | lw $v1, 0($v0) |
paul@9 | 661 | andi $v1, $v1, (1 << 9) /* T2IF */ |
paul@9 | 662 | beqz $v1, irq_dma |
paul@9 | 663 | nop |
paul@9 | 664 | |
paul@9 | 665 | /* Increment the line counter. */ |
paul@9 | 666 | |
paul@9 | 667 | addiu $s0, $s0, 1 |
paul@9 | 668 | |
paul@9 | 669 | /* Jump to the event handler. */ |
paul@9 | 670 | |
paul@9 | 671 | jalr $s1 |
paul@9 | 672 | nop |
paul@9 | 673 | |
paul@9 | 674 | irq_clear_timer: |
paul@9 | 675 | |
paul@9 | 676 | /* Clear the timer interrupt condition. */ |
paul@9 | 677 | |
paul@9 | 678 | la $v0, IFS0 |
paul@9 | 679 | li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */ |
paul@9 | 680 | sw $v1, CLR($v0) |
paul@9 | 681 | |
paul@9 | 682 | irq_dma: |
paul@9 | 683 | |
paul@9 | 684 | /* Check for a DMA interrupt condition. */ |
paul@9 | 685 | |
paul@9 | 686 | la $v0, IFS1 |
paul@9 | 687 | lw $v1, 0($v0) |
paul@9 | 688 | li $t8, (1 << 28) /* DMA0IF */ |
paul@9 | 689 | and $v1, $v1, $t8 |
paul@9 | 690 | beqz $v1, irq_exit |
paul@9 | 691 | nop |
paul@9 | 692 | |
paul@9 | 693 | /* Test the block transfer completion interrupt flag. */ |
paul@9 | 694 | |
paul@9 | 695 | la $v0, DCH0INT |
paul@9 | 696 | lw $v1, 0($v0) |
paul@9 | 697 | andi $v1, $v1, (1 << 3) /* CHBCIF */ |
paul@9 | 698 | beqz $v1, irq_clear_dma |
paul@9 | 699 | nop |
paul@9 | 700 | |
paul@9 | 701 | /* Clear the block transfer completion interrupt flag. */ |
paul@9 | 702 | |
paul@9 | 703 | li $v1, (1 << 3) /* CHBCIF = 0 */ |
paul@9 | 704 | sw $v1, CLR($v0) |
paul@9 | 705 | |
paul@9 | 706 | /* |
paul@9 | 707 | Update the line data address if the line counter (referring to the |
paul@9 | 708 | next line) is even. |
paul@9 | 709 | */ |
paul@9 | 710 | |
paul@9 | 711 | andi $t8, $s0, 1 |
paul@9 | 712 | bnez $t8, irq_clear_dma |
paul@9 | 713 | nop |
paul@9 | 714 | |
paul@9 | 715 | /* Reference the next line and update the DMA source address. */ |
paul@9 | 716 | |
paul@9 | 717 | addiu $s2, $s2, LINE_LENGTH |
paul@9 | 718 | |
paul@9 | 719 | /* Test for wraparound. */ |
paul@9 | 720 | |
paul@9 | 721 | li $t8, SCREEN_SIZE |
paul@9 | 722 | sltu $t8, $s2, $t8 |
paul@9 | 723 | bnez $t8, irq_dma_update |
paul@9 | 724 | nop |
paul@9 | 725 | |
paul@9 | 726 | /* Reset the source address. */ |
paul@9 | 727 | |
paul@9 | 728 | move $s2, $zero |
paul@9 | 729 | |
paul@9 | 730 | irq_dma_update: |
paul@9 | 731 | |
paul@9 | 732 | la $v0, DCH0SSA |
paul@9 | 733 | sw $s2, 0($v0) |
paul@9 | 734 | |
paul@9 | 735 | irq_clear_dma: |
paul@9 | 736 | |
paul@9 | 737 | /* Clear the DMA interrupt condition. */ |
paul@9 | 738 | |
paul@9 | 739 | la $v0, IFS1 |
paul@9 | 740 | li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */ |
paul@9 | 741 | sw $v1, CLR($v0) |
paul@9 | 742 | |
paul@9 | 743 | irq_exit: |
paul@9 | 744 | eret |
paul@9 | 745 | nop |
paul@9 | 746 | |
paul@9 | 747 | |
paul@9 | 748 | |
paul@9 | 749 | /* Event routines. */ |
paul@9 | 750 | |
paul@9 | 751 | /* The vertical back porch. */ |
paul@9 | 752 | |
paul@9 | 753 | vbp_active: |
paul@9 | 754 | /* Test for visible region. */ |
paul@9 | 755 | |
paul@9 | 756 | sltiu $v0, $s0, VISIBLE_START |
paul@9 | 757 | bnez $v0, _vbp_active_ret |
paul@9 | 758 | nop |
paul@9 | 759 | |
paul@9 | 760 | /* Start the visible region. */ |
paul@9 | 761 | |
paul@9 | 762 | la $s1, visible_active |
paul@9 | 763 | |
paul@9 | 764 | _vbp_active_ret: |
paul@9 | 765 | jr $ra |
paul@9 | 766 | nop |
paul@9 | 767 | |
paul@9 | 768 | |
paul@9 | 769 | |
paul@9 | 770 | /* The visible region. */ |
paul@9 | 771 | |
paul@9 | 772 | visible_active: |
paul@9 | 773 | /* Test for front porch. */ |
paul@9 | 774 | |
paul@9 | 775 | sltiu $v0, $s0, VFP_START |
paul@9 | 776 | bnez $v0, _visible_active_ret |
paul@9 | 777 | nop |
paul@9 | 778 | |
paul@9 | 779 | /* Start the front porch region. */ |
paul@9 | 780 | |
paul@9 | 781 | la $s1, vfp_active |
paul@9 | 782 | |
paul@9 | 783 | _visible_active_ret: |
paul@9 | 784 | jr $ra |
paul@9 | 785 | nop |
paul@9 | 786 | |
paul@9 | 787 | |
paul@9 | 788 | |
paul@9 | 789 | /* Within the vertical front porch. */ |
paul@9 | 790 | |
paul@9 | 791 | vfp_active: |
paul@9 | 792 | /* Test for vsync. */ |
paul@9 | 793 | |
paul@9 | 794 | sltiu $v0, $s0, VSYNC_START |
paul@9 | 795 | bnez $v0, _vfp_active_ret |
paul@9 | 796 | nop |
paul@9 | 797 | |
paul@9 | 798 | /* Start the vsync. */ |
paul@9 | 799 | |
paul@9 | 800 | la $s1, vsync_active |
paul@9 | 801 | |
paul@9 | 802 | /* Bring vsync low when the next line starts. */ |
paul@9 | 803 | |
paul@9 | 804 | la $v0, OC2CON |
paul@9 | 805 | li $v1, 0b010 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@9 | 806 | sw $v1, 0($v0) |
paul@9 | 807 | |
paul@9 | 808 | _vfp_active_ret: |
paul@9 | 809 | jr $ra |
paul@9 | 810 | nop |
paul@9 | 811 | |
paul@9 | 812 | |
paul@9 | 813 | |
paul@9 | 814 | /* The vsync period. */ |
paul@9 | 815 | |
paul@9 | 816 | vsync_active: |
paul@9 | 817 | /* Test for front porch. */ |
paul@9 | 818 | |
paul@9 | 819 | sltiu $v0, $s0, VSYNC_END |
paul@9 | 820 | bnez $v0, _vsync_active_ret |
paul@9 | 821 | nop |
paul@9 | 822 | |
paul@9 | 823 | /* Start the back porch. */ |
paul@9 | 824 | |
paul@9 | 825 | move $s0, $zero |
paul@9 | 826 | la $s1, vbp_active |
paul@9 | 827 | |
paul@9 | 828 | /* Bring vsync high when the next line starts. */ |
paul@9 | 829 | |
paul@9 | 830 | la $v0, OC2CON |
paul@9 | 831 | li $v1, 0b001 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 001 (single compare, output driven high) */ |
paul@9 | 832 | sw $v1, 0($v0) |
paul@9 | 833 | |
paul@9 | 834 | _vsync_active_ret: |
paul@9 | 835 | jr $ra |
paul@9 | 836 | nop |