73:83ebe9cd0314
60:ae02a1821af3
|
2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
|
|
mips.h vga.S
|
|
72:a297782bef19
82:f83509c62e12
70:129ef681b3fc
|
2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Reordered channel and timer activation instructions, tidied generally. |
|
|
vga.S
|
|
71:0c6e88eb049f
75:7edceda19310
69:aa1ac5755f03
|
2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Reordered channel and timer activation instructions, tidied generally. |
|
|
vga.S
|
|
70:129ef681b3fc
72:a297782bef19
66:64546519a57d
|
2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
|
|
mips.h vga.S
|
|
69:aa1ac5755f03
71:0c6e88eb049f
53:9b3b13a62733
|
2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
|
|
mips.h vga.S
|
|
68:ec19e9f803b5
|
2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
|
Enable Timer3 interrupts in order to create timer events. |
|
|
pic32.h vga.S
|
|
67:22ebe789d830
|
2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
|
Double the peripheral clock frequency for further timer usage. |
|
|
vga.S vga.h
|
|
66:64546519a57d
67:22ebe789d830 70:129ef681b3fc
|
2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
|
Removed superfluous interrupt handling. |
|
|
vga.S
|
|
65:51c387b05002
|
2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
|
Disabled the reset channel interrupt which appears superfluous for chaining as
well as needing to be handled at the CPU level. |
|
|
vga.S
|
|
64:0f2d331ec834
59:5d02b5c6d920
|
2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
|
Test usage of Timer3 to initiate the reset channel cell transfer. |
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|
vga.S
|
|