82:f83509c62e12
84:ef577181c119
72:a297782bef19 81:2bc674143b08
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2017-11-19 |
Paul Boddie |
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Merged changes from a parallel development branch. |
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vga.S
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81:2bc674143b08
82:f83509c62e12 83:0a7176ba81ef 85:078c1d57677c
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2017-11-19 |
Paul Boddie |
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Save and restore $gp so that the text blitting functions do not cause crashes. |
snapshot-20171119 |
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vga.S vga.h
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80:6272f9be2733
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2017-11-18 |
Paul Boddie |
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Fixed declarations. |
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vga.S
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79:2e0a0e847898
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2017-11-18 |
Paul Boddie |
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Moved exception handler to the end. |
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vga.S
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78:389d1792af4a
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2017-11-18 |
Paul Boddie |
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Introduced macros to ensure register saving and loading consistency. |
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vga.S
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77:61443a9bb80f
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2017-11-18 |
Paul Boddie |
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Introduced UART usage to obtain exception details. |
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mips.h pic32.h vga.S
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76:ff962c071724
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2017-11-17 |
Paul Boddie |
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Update timer interrupt priorities atomically, removing disable/enable code. |
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vga.S
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75:7edceda19310
71:0c6e88eb049f
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2017-11-16 |
Paul Boddie |
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Reorganised interrupt handling to only test either timer or DMA interrupt
conditions, not both, also merging the execution of the visible/active region
and address update routines within a single call. |
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vga.S
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74:7d1685074d4c
83:0a7176ba81ef
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2017-11-07 |
Paul Boddie |
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Reordered channel and timer activation instructions, tidied generally. |
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vga.S
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73:83ebe9cd0314
60:ae02a1821af3
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2017-11-07 |
Paul Boddie |
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Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
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mips.h vga.S
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