1.1 --- a/README.txt Sat Nov 04 17:07:15 2017 +0100
1.2 +++ b/README.txt Sat Nov 04 17:47:52 2017 +0100
1.3 @@ -38,8 +38,8 @@
1.4 D2/RB2 6 23
1.5 D3/RB3 7 22 RB11/PGEC2
1.6 8 21 RB10/PGEC3
1.7 - RA2 9 20
1.8 - CLKO/RA3 10 19
1.9 + REFCLKO/RA2 9 20
1.10 + RA3 10 19
1.11 D4/RB4 11 18 RB9
1.12 12 17 RB8
1.13 13 16 RB7/D7
1.14 @@ -50,7 +50,7 @@
1.15 Clock Output Routing
1.16 --------------------
1.17
1.18 -CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.19 +REFCLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.20 data signals then routed through the flip-flop as follows:
1.21
1.22 MR# 1 \/ 20 VCC
1.23 @@ -62,7 +62,7 @@
1.24 in D2/D2 7 14 D5/D5 in
1.25 in D3/D3 8 13 D4/D4 in
1.26 out D3/Q3 9 12 Q4/D4 out
1.27 - GND 10 11 CP/CLKO in
1.28 + GND 10 11 CP/REFCLKO in
1.29
1.30 MR# is kept at a high level. All out signals are then supplied to the
1.31 analogue circuit provided below.