1.1 --- a/vga.S Sat Nov 04 17:07:15 2017 +0100
1.2 +++ b/vga.S Sat Nov 04 17:47:52 2017 +0100
1.3 @@ -40,8 +40,7 @@
1.4 */
1.5
1.6 .section .devcfg1, "a"
1.7 -.word 0xff7fd8d9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.8 - DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
1.9 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.10 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.11
1.12 /*
1.13 @@ -122,6 +121,9 @@
1.14 jal init_io_pins
1.15 nop
1.16
1.17 + jal init_refclk_pins
1.18 + nop
1.19 +
1.20 /* Initialise the status register. */
1.21
1.22 jal init_interrupts
1.23 @@ -382,6 +384,42 @@
1.24
1.25
1.26
1.27 +/*
1.28 +Clock output initialisation. The peripheral clock divided by 2 is output via the
1.29 +CLKO pin to drive a flip-flop.
1.30 +*/
1.31 +
1.32 +init_refclk_pins:
1.33 + /* Change the output clock frequency. */
1.34 +
1.35 + la $v0, REFOCON
1.36 + li $v1, (0b1001001 << 9)
1.37 + sw $v1, SET($v0) /* REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<9> = DIVSWEN = 1 */
1.38 +
1.39 +_refclk_wait:
1.40 + lw $v1, 0($v0)
1.41 + andi $v1, $v1, (1 << 8) /* REFOCON<8> = ACTIVE */
1.42 + bnez $v1, _refclk_wait
1.43 + nop
1.44 +
1.45 + li $v1, 0b1111 /* ROSEL<3:0> = 0000 */
1.46 + sw $v1, CLR($v0)
1.47 + li $v1, 0b0001 /* ROSEL<3:0> = 0001 (PBCLK) */
1.48 + sw $v1, SET($v0)
1.49 +
1.50 + /*
1.51 + The RODIV and ROTRIM values should be zero by default, yielding a
1.52 + frequency of half the input indicated by ROSEL.
1.53 + */
1.54 +
1.55 + li $v1, (1 << 9) /* REFOCON<9> = DIVSWEN = 0 */
1.56 + sw $v1, CLR($v0)
1.57 +
1.58 + jr $ra
1.59 + nop
1.60 +
1.61 +
1.62 +
1.63 init_io_pins:
1.64 /* Unlock the configuration register bits. */
1.65