1.1 --- a/vga.h Sun May 28 19:11:01 2017 +0200
1.2 +++ b/vga.h Sun May 28 22:02:02 2017 +0200
1.3 @@ -1,19 +1,25 @@
1.4 #ifndef __VGA_H__
1.5 #define __VGA_H__
1.6
1.7 -#define LINE_LENGTH 160 /* pixels */
1.8 -#define LINE_COUNT 256 /* distinct display lines */
1.9 +#define LINE_LENGTH 160 /* pixels */
1.10 +#define LINE_COUNT 256 /* distinct display lines */
1.11
1.12 -#define HFREQ_LIMIT 643 /* 24MHz cycles */
1.13 -#define HSYNC_START 460 /* 24MHz cycles */
1.14 -#define HSYNC_LIMIT 64 /* 24MHz cycles */
1.15 +#define HFREQ_LIMIT 643 /* 24MHz cycles */
1.16 +#define HSYNC_START 460 /* 24MHz cycles */
1.17 +#define HSYNC_LIMIT 64 /* 24MHz cycles */
1.18 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
1.19
1.20 -#define VISIBLE_START 70 /* horizontal lines, back porch end */
1.21 +#define VISIBLE_START 70 /* horizontal lines, back porch end */
1.22 #define VFP_START (VISIBLE_START + 2 * LINE_COUNT)
1.23 -#define VSYNC_START 620 /* horizontal lines, front porch end */
1.24 -#define VSYNC_END 622 /* horizontal lines, back porch start */
1.25 +#define VSYNC_START 620 /* horizontal lines, front porch end */
1.26 +#define VSYNC_END 622 /* horizontal lines, back porch start */
1.27
1.28 +#define SCREEN_BASE 256
1.29 #define SCREEN_SIZE (40 * 1024)
1.30
1.31 +#define SCREEN_BASE_KSEG0 (KSEG0_BASE + SCREEN_BASE)
1.32 +
1.33 +#define IRQ_STACK_LIMIT SCREEN_BASE_KSEG0
1.34 +#define IRQ_STACK_TOP (IRQ_STACK_LIMIT - 56)
1.35 +
1.36 #endif /* __VGA_H__ */