1.1 --- a/vga.S Fri Nov 03 23:25:06 2017 +0100
1.2 +++ b/vga.S Tue Nov 07 14:04:29 2017 +0100
1.3 @@ -284,8 +284,6 @@
1.4 la $v0, IPC2
1.5 li $v1, 0b11111
1.6 sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.7 -
1.8 - la $v0, IPC2
1.9 li $v1, 0b11111
1.10 sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
1.11
1.12 @@ -628,6 +626,7 @@
1.13 mfc0 $t3, CP0_STATUS
1.14 li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */
1.15 and $t3, $t3, $t4
1.16 + ori $t3, $t3, (3 << STATUS_IRQ_SHIFT)
1.17 li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
1.18 and $t3, $t3, $t4
1.19 ori $t3, $t3, STATUS_IE
1.20 @@ -890,12 +889,25 @@
1.21 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
1.22 sw $v1, SET($v0)
1.23
1.24 - /* Disable the timer interrupt during the visible period. */
1.25 + /*
1.26 + Suspend delivery of the timer interrupt during the visible period.
1.27 + The condition still occurs, however.
1.28 + */
1.29
1.30 la $v0, IEC0
1.31 li $v1, (1 << 9)
1.32 sw $v1, CLR($v0) /* T2IE = 0 */
1.33
1.34 + la $v0, IPC2
1.35 + li $v1, 0b11111
1.36 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.37 + li $v1, 0b00111
1.38 + sw $v1, SET($v0) /* T2IP = 1; T2IS = 3 */
1.39 +
1.40 + la $v0, IEC0
1.41 + li $v1, (1 << 9)
1.42 + sw $v1, SET($v0) /* T2IE = 0 */
1.43 +
1.44 _vbp_active_ret:
1.45 jr $ra
1.46 nop
1.47 @@ -915,7 +927,17 @@
1.48
1.49 la $s1, vfp_active
1.50
1.51 - /* Re-enable the timer interrupt after the visible period. */
1.52 + /* Restore delivery of the timer interrupt after the visible period. */
1.53 +
1.54 + la $v0, IEC0
1.55 + li $v1, (1 << 9)
1.56 + sw $v1, CLR($v0) /* T2IE = 0 */
1.57 +
1.58 + la $v0, IPC2
1.59 + li $v1, 0b11111
1.60 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.61 + li $v1, 0b11111
1.62 + sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
1.63
1.64 la $v0, IEC0
1.65 li $v1, (1 << 9)