1.1 --- a/README.txt Fri Nov 03 23:25:06 2017 +0100
1.2 +++ b/README.txt Sat Nov 04 17:07:15 2017 +0100
1.3 @@ -39,7 +39,7 @@
1.4 D3/RB3 7 22 RB11/PGEC2
1.5 8 21 RB10/PGEC3
1.6 RA2 9 20
1.7 - RA3 10 19
1.8 + CLKO/RA3 10 19
1.9 D4/RB4 11 18 RB9
1.10 12 17 RB8
1.11 13 16 RB7/D7
1.12 @@ -47,6 +47,26 @@
1.13
1.14 Note that RB6 is not available on pin 15 on this device.
1.15
1.16 +Clock Output Routing
1.17 +--------------------
1.18 +
1.19 +CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.20 +data signals then routed through the flip-flop as follows:
1.21 +
1.22 + MR# 1 \/ 20 VCC
1.23 + out D0/Q0 2 19 Q7/D7 out
1.24 + in D0/D0 3 18 D7/D7 in
1.25 + in D1/D1 4 17 D6
1.26 + out D1/Q1 5 16 Q6
1.27 + out D2/Q2 6 15 Q5/D5 out
1.28 + in D2/D2 7 14 D5/D5 in
1.29 + in D3/D3 8 13 D4/D4 in
1.30 + out D3/Q3 9 12 Q4/D4 out
1.31 + GND 10 11 CP/CLKO in
1.32 +
1.33 +MR# is kept at a high level. All out signals are then supplied to the
1.34 +analogue circuit provided below.
1.35 +
1.36 Data Signal Routing
1.37 -------------------
1.38