1.1 --- a/vga.S Fri Nov 03 23:25:06 2017 +0100
1.2 +++ b/vga.S Sat Nov 04 17:07:15 2017 +0100
1.3 @@ -32,12 +32,16 @@
1.4
1.5 The watchdog timer (FWDTEN) is also disabled.
1.6
1.7 +The primary oscillator is configured to provide an external clock and CLKO
1.8 +output is enabled.
1.9 +
1.10 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.11 RPB4.
1.12 */
1.13
1.14 .section .devcfg1, "a"
1.15 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.16 +.word 0xff7fd8d9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.17 + DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
1.18 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.19
1.20 /*
1.21 @@ -115,7 +119,7 @@
1.22 li $t1, (1 << 3) /* PORTA<3> = RA3 */
1.23 sw $t1, CLR($t0)
1.24
1.25 - jal init_oc_pins
1.26 + jal init_io_pins
1.27 nop
1.28
1.29 /* Initialise the status register. */
1.30 @@ -376,7 +380,9 @@
1.31 jr $ra
1.32 nop
1.33
1.34 -init_oc_pins:
1.35 +
1.36 +
1.37 +init_io_pins:
1.38 /* Unlock the configuration register bits. */
1.39
1.40 la $v0, SYSKEY
1.41 @@ -403,6 +409,14 @@
1.42 li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */
1.43 sw $v1, 0($v0)
1.44
1.45 + /* Map REFCLKO to RPA2. */
1.46 +
1.47 + la $v0, RPA2R
1.48 + li $v1, 0b0111 /* RPA2R<3:0> = 0111 (REFCLKO) */
1.49 + sw $v1, 0($v0)
1.50 +
1.51 + /* Restore CFGCON. */
1.52 +
1.53 la $v0, CFGCON
1.54 sw $t8, 0($v0)
1.55