VGAPIC32

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Added tag snapshot-20171120 for changeset c9ec1da2c3ca default tip
Added tag snapshot-20171119 for changeset 2bc674143b08
Merged changes from a parallel development branch.
Enable and disable the DMA channel rather than changing IRQ settings. snapshot-20171120
Merged changes from a parallel development branch.
Remove superfluous CHAED (receive events when disabled) flag. Minor tidying.
Remove apparently superfluous Timer3 interrupt initialisation.
Merged changes from a parallel development branch.
Remove apparently superfluous Timer2 interrupt initialisation.
Merged changes from a parallel development branch. Retained DMA interrupt usage
Invoke the display state machine using output compare interrupts instead of a
Enable the Timer3 interrupt at low priority.
Merged changes from a parallel development branch. The result is still broken.
Merged changes from a parallel development branch.
Save and restore $gp so that the text blitting functions do not cause crashes. snapshot-20171119
Fixed declarations.
Moved exception handler to the end.
Introduced macros to ensure register saving and loading consistency.
Introduced UART usage to obtain exception details.
Update timer interrupt priorities atomically, removing disable/enable code.
Reorganised interrupt handling to only test either timer or DMA interrupt
Reordered channel and timer activation instructions, tidied generally.
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
Reordered channel and timer activation instructions, tidied generally.
Reordered channel and timer activation instructions, tidied generally.
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
Enable Timer3 interrupts in order to create timer events.
Double the peripheral clock frequency for further timer usage.
Removed superfluous interrupt handling.
Disabled the reset channel interrupt which appears superfluous for chaining as
Test usage of Timer3 to initiate the reset channel cell transfer.
Test usage of Timer3 to initiate the reset channel cell transfer.
Test usage of Timer3 to initiate the reset channel cell transfer.
A tentative sketch of how OC3 might drive line DMA transfers and the clock pulse
Make DMA channel 1 the line channel. Things will only now work if the Timer2
Test chaining of DMA channels, adding one between the line and reset channels.
Make DMA channel 1 the line channel. Things will only now work if the Timer2 CLKO-to-74HC273-CP
Test chaining of DMA channels, adding one between the line and reset channels. CLKO-to-74HC273-CP
Simplify REFCLKO initialisation and set RODIV to 2 to test pixel uniformity. CLKO-to-74HC273-CP
Switch to REFCLKO instead of using CLKO and the primary oscillator. CLKO-to-74HC273-CP
Experiment with the use of CLKO providing the clock pulse of a flip-flop CLKO-to-74HC273-CP
Removed redundant operations such as loads whose values are already loaded.
Removed redundant operations such as loads whose values are already loaded.
Change the DMA channels used from 0 and 1 to 1 and 2.
Fixed DMA channel 2 registers. Reformatted and added some more definitions.
Fixed comments.
Added some comments.
Disable the timer interrupt in order to reduce memory contention with the line
Disable the line channel only when its completion is being handled.
Created a separate DMA address update routine. Note that it does not use $ra
Simplified the interrupt handler slightly.
Reset the DMA source address for the first line, even though it is not necessary
Disable and re-enable the line channel when setting the source address, even
Put character string, font and image data into separate files.
Added a tool to generate font definitions from GNU Unifont definitions.
Transition between the picture and the pattern.
Added register and display state saving and retrieval in the interrupt handler.
Write to KSEG0 instead of KSEG1.
Moved the framebuffer copying routine into a separate function.
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