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Enable Timer3 interrupts in order to create timer events. |
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Double the peripheral clock frequency for further timer usage. |
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Removed superfluous interrupt handling. |
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Disabled the reset channel interrupt which appears superfluous for chaining as |
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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A tentative sketch of how OC3 might drive line DMA transfers and the clock pulse |
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Make DMA channel 1 the line channel. Things will only now work if the Timer2 |
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Test chaining of DMA channels, adding one between the line and reset channels. |
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Make DMA channel 1 the line channel. Things will only now work if the Timer2 |
CLKO-to-74HC273-CP |
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Test chaining of DMA channels, adding one between the line and reset channels. |
CLKO-to-74HC273-CP |
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Simplify REFCLKO initialisation and set RODIV to 2 to test pixel uniformity. |
CLKO-to-74HC273-CP |
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Switch to REFCLKO instead of using CLKO and the primary oscillator. |
CLKO-to-74HC273-CP |
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Experiment with the use of CLKO providing the clock pulse of a flip-flop |
CLKO-to-74HC273-CP |
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Removed redundant operations such as loads whose values are already loaded. |
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Removed redundant operations such as loads whose values are already loaded. |
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Change the DMA channels used from 0 and 1 to 1 and 2. |
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Fixed DMA channel 2 registers. Reformatted and added some more definitions. |
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Fixed comments. |
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Added some comments. |
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Disable the timer interrupt in order to reduce memory contention with the line |
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Disable the line channel only when its completion is being handled. |
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Created a separate DMA address update routine. Note that it does not use $ra |
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Simplified the interrupt handler slightly. |
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Reset the DMA source address for the first line, even though it is not necessary |
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Disable and re-enable the line channel when setting the source address, even |
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Put character string, font and image data into separate files. |
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Added a tool to generate font definitions from GNU Unifont definitions. |
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Transition between the picture and the pattern. |
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Added register and display state saving and retrieval in the interrupt handler. |
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Write to KSEG0 instead of KSEG1. |
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Moved the framebuffer copying routine into a separate function. |
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Moved display definitions and framebuffer pattern generation to separate files. |
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Initialise system state before starting interrupts, preventing exceptions caused |
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Put the general exception handler in the proper location. |
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Added a link to an article about the project. |
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Added diagrams showing VGA signal, DMA transfer, and output circuit details. |
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Fixed sync pin assignment details. |
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Updated the circuit information. |
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Added a test pattern generating routine. |
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Fixed the number of visible display lines. |
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Updated the image to feature dithering and more realistic colours. |
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Use a suitable image for the I0RRGGBB representation. |
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Added copyright and licensing information. |
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Switched to using a I0RRGGBB colour representation. |
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Added a tool for simple image conversion to the appropriate pixel data format. |
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Test a 48MHz system clock, 24MHz peripheral clock, and 800 x 600 @ 60Hz output |
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Added missing operations to enable and disable the line channel. |
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Updated the documentation to indicate that RB6 is not available and that only |
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Added example image data and a sync instruction that seems to help the CPU |
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Introduced a screen start address register. |
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Fill the display by using a 30MHz clock and adjusted timings. |
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Switched to using PORTB instead of PMDIN for pixel data output. |
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Update the cache status in the config register. |
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Added initial documentation. |
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Fixed bitfield information in comment. |
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Tidied up the comments somewhat. |
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Simplified the horizontal line details; introduced bus arbitration mode 2 usage. |
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Introduced interrupt and exception initialisation fixes plus a revised state |
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