# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509988332 -3600
# Node ID 0f2d331ec8342bf7c890257b7f2bcd4fe4dc14de
# Parent  5d02b5c6d920767172ddbc54c075d7d891f68da6
Test usage of Timer3 to initiate the reset channel cell transfer.

diff -r 5d02b5c6d920 -r 0f2d331ec834 vga.S
--- a/vga.S	Sat Nov 04 21:33:58 2017 +0100
+++ b/vga.S	Mon Nov 06 18:12:12 2017 +0100
@@ -133,7 +133,7 @@
 
 	/* Initialise timer. */
 
-	jal init_timer2
+	jal init_timers
 	nop
 
 	/* Initialise DMA. */
@@ -260,7 +260,7 @@
 
 /* Initialisation routines. */
 
-init_timer2:
+init_timers:
 
 	/* Initialise Timer2 for sync pulses. */
 
@@ -299,6 +299,25 @@
 	li $v1, (1 << 15)
 	sw $v1, SET($v0)	/* ON = 1 */
 
+	/* Initialise Timer3 for line DMA cell transfer. */
+
+	la $v0, T3CON
+	sw $zero, 0($v0)	/* T3CON = 0 */
+	nop
+
+	la $v0, TMR3
+	sw $zero, 0($v0)	/* TMR3 = 0 */
+
+	la $v0, PR3
+	li $v1, 1
+	sw $v1, 0($v0)		/* PR3 = 1 */
+
+	/* Start timer. */
+
+	la $v0, T3CON
+	li $v1, (1 << 15)
+	sw $v1, SET($v0)	/* ON = 1 */
+
 	jr $ra
 	nop
 
@@ -495,17 +514,18 @@
 	sw $v1, 0($v0)
 
 	/*
-	Initiate reset channel transfer when channel 0 is finished:
-	DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt
+	Initiate reset channel transfer when channel 0 is finished;
+	timer 3 causes cell transfers:
+	DCHxECON<15:8> = CHSIRQ<7:0> = timer 3 interrupt
 	DCHxECON<4> = SIRQEN = 1
 	*/
 
 	la $v0, DCH1ECON
-	li $v1, (60 << 8) | (1 << 4)
+	li $v1, (14 << 8) | (1 << 4)
 	sw $v1, 0($v0)
 
 	la $v0, DCH2ECON
-	li $v1, (61 << 8) | (1 << 4)
+	li $v1, (14 << 8) | (1 << 4)
 	sw $v1, 0($v0)
 
 	/*