# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509991967 -3600
# Node ID 22ebe789d8303650c2378a119e5f1f3302a51de4
# Parent  64546519a57de32cf2a7ab96b56010bdde97a9dd
Double the peripheral clock frequency for further timer usage.

diff -r 64546519a57d -r 22ebe789d830 vga.S
--- a/vga.S	Mon Nov 06 19:12:01 2017 +0100
+++ b/vga.S	Mon Nov 06 19:12:47 2017 +0100
@@ -28,7 +28,7 @@
 
 /*
 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
-divided by 2, and FRCDIV+PLL selected.
+divided by 1, and FRCDIV+PLL selected.
 
 The watchdog timer (FWDTEN) is also disabled.
 
@@ -37,7 +37,7 @@
 */
 
 .section .devcfg1, "a"
-.word 0xff7fdfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
+.word 0xff7fcfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 0;
 			DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
 
 /*
diff -r 64546519a57d -r 22ebe789d830 vga.h
--- a/vga.h	Mon Nov 06 19:12:01 2017 +0100
+++ b/vga.h	Mon Nov 06 19:12:47 2017 +0100
@@ -4,9 +4,9 @@
 #define LINE_LENGTH	160				/* pixels */
 #define LINE_COUNT	256				/* distinct display lines */
 
-#define HFREQ_LIMIT	643				/* 24MHz cycles */
-#define HSYNC_START	460				/* 24MHz cycles */
-#define HSYNC_LIMIT	64				/* 24MHz cycles */
+#define HFREQ_LIMIT	1286				/* 48MHz cycles */
+#define HSYNC_START	920				/* 48MHz cycles */
+#define HSYNC_LIMIT	128				/* 48MHz cycles */
 #define HSYNC_END	(HSYNC_START + HSYNC_LIMIT)
 
 #define VISIBLE_START	70				/* horizontal lines, back porch end */