# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509814072 -3600
# Node ID 426ff3c6a4dab592a04c2f7956c3369ada98abb5
# Parent  d782a0c62e19523c34afb06b18bd541dcaa3113e
Switch to REFCLKO instead of using CLKO and the primary oscillator.

diff -r d782a0c62e19 -r 426ff3c6a4da README.txt
--- a/README.txt	Sat Nov 04 17:07:15 2017 +0100
+++ b/README.txt	Sat Nov 04 17:47:52 2017 +0100
@@ -38,8 +38,8 @@
        D2/RB2  6      23
        D3/RB3  7      22 RB11/PGEC2
                8      21 RB10/PGEC3
-          RA2  9      20
-     CLKO/RA3 10      19
+  REFCLKO/RA2  9      20
+          RA3 10      19
        D4/RB4 11      18 RB9
               12      17 RB8
               13      16 RB7/D7
@@ -50,7 +50,7 @@
 Clock Output Routing
 --------------------
 
-CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
+REFCLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
 data signals then routed through the flip-flop as follows:
 
           MR#  1  \/  20 VCC
@@ -62,7 +62,7 @@
      in D2/D2  7      14 D5/D5 in
      in D3/D3  8      13 D4/D4 in
     out D3/Q3  9      12 Q4/D4 out
-          GND 10      11 CP/CLKO in
+          GND 10      11 CP/REFCLKO in
 
 MR# is kept at a high level. All out signals are then supplied to the
 analogue circuit provided below.
diff -r d782a0c62e19 -r 426ff3c6a4da vga.S
--- a/vga.S	Sat Nov 04 17:07:15 2017 +0100
+++ b/vga.S	Sat Nov 04 17:47:52 2017 +0100
@@ -40,8 +40,7 @@
 */
 
 .section .devcfg1, "a"
-.word 0xff7fd8d9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
-			DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
+.word 0xff7fdfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
 			DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
 
 /*
@@ -122,6 +121,9 @@
 	jal init_io_pins
 	nop
 
+	jal init_refclk_pins
+	nop
+
 	/* Initialise the status register. */
 
 	jal init_interrupts
@@ -382,6 +384,42 @@
 
 
 
+/*
+Clock output initialisation. The peripheral clock divided by 2 is output via the
+CLKO pin to drive a flip-flop.
+*/
+
+init_refclk_pins:
+	/* Change the output clock frequency. */
+
+	la $v0, REFOCON
+	li $v1, (0b1001001 << 9)
+	sw $v1, SET($v0)	/* REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<9> = DIVSWEN = 1 */
+
+_refclk_wait:
+	lw $v1, 0($v0)
+	andi $v1, $v1, (1 << 8)	/* REFOCON<8> = ACTIVE */
+	bnez $v1, _refclk_wait
+	nop
+
+	li $v1, 0b1111		/* ROSEL<3:0> = 0000 */
+	sw $v1, CLR($v0)
+	li $v1, 0b0001		/* ROSEL<3:0> = 0001 (PBCLK) */
+	sw $v1, SET($v0)
+
+	/*
+	The RODIV and ROTRIM values should be zero by default, yielding a
+	frequency of half the input indicated by ROSEL.
+	*/
+
+	li $v1, (1 << 9)	/* REFOCON<9> = DIVSWEN = 0 */
+	sw $v1, CLR($v0)
+
+	jr $ra
+	nop
+
+
+
 init_io_pins:
 	/* Unlock the configuration register bits. */