# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1511023992 -3600
# Node ID 61443a9bb80feff0c37e146a463fb61a14c0de85
# Parent  ff962c071724be815dd11aeb37afc5345881e955
Introduced UART usage to obtain exception details.

diff -r ff962c071724 -r 61443a9bb80f mips.h
--- a/mips.h	Fri Nov 17 17:22:46 2017 +0100
+++ b/mips.h	Sat Nov 18 17:53:12 2017 +0100
@@ -10,6 +10,7 @@
 #define CP0_CONTEXT	$4
 #define CP0_PAGEMASK	$5
 #define CP0_WIRED	$6
+#define CP0_BADVADDR	$8
 #define CP0_COUNT	$9
 #define CP0_ENTRYHI	$10
 #define CP0_COMPARE	$11
diff -r ff962c071724 -r 61443a9bb80f pic32.h
--- a/pic32.h	Fri Nov 17 17:22:46 2017 +0100
+++ b/pic32.h	Sat Nov 18 17:53:12 2017 +0100
@@ -28,6 +28,12 @@
 #define TMR3    	0xBF800A10
 #define PR3     	0xBF800A20
 
+#define U1MODE		0xBF806000
+#define U1STA		0xBF806010
+#define U1TXREG		0xBF806020
+#define U1RXREG		0xBF806030
+#define U1BRG		0xBF806040
+
 #define PMCON 		0xBF807000
 #define PMMODE		0xBF807010
 #define PMADDR		0xBF807020
@@ -42,6 +48,8 @@
 #define CFGCON		0xBF80F200
 #define SYSKEY		0xBF80F230
 
+#define U1RXR		0xBF80FA50
+
 #define RPA0R		0xBF80FB00
 #define RPA1R		0xBF80FB04
 #define RPA2R		0xBF80FB08
@@ -54,6 +62,7 @@
 #define RPB4R		0xBF80FB3C
 #define RPB5R		0xBF80FB40
 #define RPB10R		0xBF80FB54
+#define RPB15R		0xBF80FB68
 
 #define INTCON		0xBF881000
 #define IFS0		0xBF881030
diff -r ff962c071724 -r 61443a9bb80f vga.S
--- a/vga.S	Fri Nov 17 17:22:46 2017 +0100
+++ b/vga.S	Sat Nov 18 17:53:12 2017 +0100
@@ -115,7 +115,7 @@
 	li $t1, (1 << 3)	/* PORTA<3> = RA3 */
 	sw $t1, CLR($t0)
 
-	jal init_oc_pins
+	jal init_io_pins
 	nop
 
 	/* Initialise the status register. */
@@ -146,6 +146,11 @@
 	jal init_oc
 	nop
 
+	/* Initialise UART for debugging. */
+
+	jal init_uart
+	nop
+
 	/* Initialise the display state. */
 
 	li $s0, 0		/* line counter */
@@ -186,6 +191,10 @@
 	li $t1, (1 << 3)	/* PORTA<3> = RA3 */
 	sw $t1, INV($t0)
 
+        la $v0, U1TXREG
+	li $v1, '.'
+        sw $v1, 0($v0)
+
 	bnez $a1, loop		/* until counter == 0 */
 	nop
 
@@ -374,7 +383,7 @@
 	jr $ra
 	nop
 
-init_oc_pins:
+init_io_pins:
 	/* Unlock the configuration register bits. */
 
 	la $v0, SYSKEY
@@ -401,6 +410,12 @@
 	li $v1, 0b0101		/* RPA1R<3:0> = 0101 (OC2) */
 	sw $v1, 0($v0)
 
+	/* Map U1TX to RPB15. */
+
+	la $v0, RPB15R
+	li $v1, 0b0001		/* RPB15R<3:0> = 0001 (U1TX) */
+	sw $v1, 0($v0)
+
 	la $v0, CFGCON
 	sw $t8, 0($v0)
 
@@ -612,6 +627,34 @@
 
 
 
+/* UART initialisation. */
+
+init_uart:
+        /* Initialise UART. */
+
+	la $v0, U1BRG
+	li $v1, 12			/* U1BRG<15:0> = BRG = (FPB / (16 * baudrate)) - 1 = (24000000 / (16 * 115200)) - 1 = 12 */
+	sw $v1, 0($v0)
+
+	la $v0, U1MODE
+	li $v1, (1 << 15)		/* U1MODE<15> = ON = 0 */
+	sw $v1, CLR($v0)
+
+	/* Start UART. */
+
+	la $v0, U1STA
+	li $v1, (1 << 10)		/* U1STA<10> = UTXEN = 1 */
+	sw $v1, SET($v0)
+
+	la $v0, U1MODE
+	li $v1, (1 << 15)		/* U1MODE<15> = ON = 1 */
+	sw $v1, SET($v0)
+
+	jr $ra
+	nop
+
+
+
 /* Utilities. */
 
 handle_error_level:
@@ -796,44 +839,38 @@
 
 
 
+/* Exception handler. */
+
 exc_handler:
-	li $t9, 0x80000000
-	mfc0 $t6, CP0_ERROREPC
+	mfc0 $t7, CP0_ERROREPC
 	nop
+
+exc_write_word:
+	li $t8, 32
+        la $v0, U1TXREG
 exc_loop:
-	and $t7, $t9, $t6
-	beqz $t7, exc_errorepc_zero
-	nop
-exc_errorepc_one:
-	la $v0, PORTA
-	li $v1, (1 << 2)	/* PORTA<2> = RA2 */
-	sw $v1, SET($v0)
-	j exc_loop_wait
+	addiu $t8, $t8, -4
+	srlv $v1, $t7, $t8	/* $v1 = $t7 >> $t8 */
+	andi $v1, $v1, 0xF
+	addiu $t9, $v1, -10	/* $t9 >= 10? */
+	bgez $t9, exc_alpha
 	nop
-exc_errorepc_zero:
-	la $v0, PORTA
-	li $v1, (1 << 3)	/* PORTA<3> = RA3 */
-	sw $v1, SET($v0)
-exc_loop_wait:
-	li $t8, 5000000
-exc_loop_delay:
-	addiu $t8, $t8, -1
-	bnez $t8, exc_loop_delay
+exc_digit:
+	addiu $v1, $v1, 48	/* convert to digit: '0' */
+	j exc_write
 	nop
-	la $v0, PORTA
-	li $v1, (3 << 2)	/* PORTA<3:2> = RA3, RA2 */
-	sw $v1, CLR($v0)
-exc_loop_wait_again:
-	li $t8, 2500000
-exc_loop_delay_again:
-	addiu $t8, $t8, -1
-	bnez $t8, exc_loop_delay_again
+exc_alpha:
+	addiu $v1, $v1, 55	/* convert to alpha: 'A' - 10 */
+exc_write:
+        sw $v1, 0($v0)
+	bnez $t8, exc_loop
 	nop
-exc_errorepc_next:
-	srl $t9, $t9, 1
-	bnez $t9, exc_loop
-	nop
-	j exc_handler
+exc_loop_end:
+	li $v1, '\n'
+        sw $v1, 0($v0)
+
+exc_handler_end:
+	j exc_handler_end
 	nop