# HG changeset patch # User Paul Boddie # Date 1506715811 -7200 # Node ID 70fc39a067073463413eca7de481a871c9193009 # Parent 466e83cd82b7b2234be2006fd13eb5b1d85f7234 Added some comments. diff -r 466e83cd82b7 -r 70fc39a06707 vga.S --- a/vga.S Sat Jun 03 22:53:06 2017 +0200 +++ b/vga.S Fri Sep 29 22:10:11 2017 +0200 @@ -69,8 +69,14 @@ la $v0, BMXCON lw $v1, 0($v0) + + /* Set zero wait states for address setup. */ + li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */ and $v1, $v1, $t8 + + /* Set bus arbitration mode. */ + li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */ ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */ and $v1, $v1, $t8 @@ -307,7 +313,8 @@ suitable start and end values. Using OC2, Timer 2 triggers a level shifting event and OC2 is reconfigured to -reverse the level at a later point. +reverse the level at a later point. In this way, the vsync pulse is generated +and is synchronised to the display lines. */ init_oc: @@ -369,7 +376,6 @@ jr $ra nop - init_oc_pins: /* Unlock the configuration register bits. */ @@ -718,8 +724,8 @@ sw $v1, CLR($v0) /* - The timer interrupt will only occur active outside the visible region, - but the interrupt condition will still occur as the timer wraps around. + The timer interrupt will only occur outside the visible region, but the + interrupt condition will still occur as the timer wraps around. Therefore, the handling of other interrupts may find the timer interrupt condition set. @@ -881,10 +887,10 @@ la $v0, DCH0SSA sw $s2, 0($v0) - /* Enable the line channel. */ + /* Enable the line channel for timer event transfer initiation. */ la $v0, DCH0ECON - li $v1, (1 << 4) + li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */ sw $v1, SET($v0) /* Disable the timer interrupt during the visible period. */ @@ -943,7 +949,7 @@ /* Disable the line channel. */ la $v0, DCH0ECON - li $v1, (1 << 4) + li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */ sw $v1, CLR($v0) j _visible_update_ret