# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509819049 -3600
# Node ID 949e2005de1c019fcf94bc3f8a88ff1a5894fd5e
# Parent  426ff3c6a4dab592a04c2f7956c3369ada98abb5
Simplify REFCLKO initialisation and set RODIV to 2 to test pixel uniformity.

diff -r 426ff3c6a4da -r 949e2005de1c vga.S
--- a/vga.S	Sat Nov 04 17:47:52 2017 +0100
+++ b/vga.S	Sat Nov 04 19:10:49 2017 +0100
@@ -390,11 +390,18 @@
 */
 
 init_refclk_pins:
-	/* Change the output clock frequency. */
+	/*
+	Change the output clock frequency.
+
+	The RODIV and ROTRIM values should be zero by default, yielding a
+	frequency of half the input indicated by ROSEL.
+
+	REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<30:16> = RODIV<14:0> = 2
+	*/
 
 	la $v0, REFOCON
-	li $v1, (0b1001001 << 9)
-	sw $v1, SET($v0)	/* REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<9> = DIVSWEN = 1 */
+	li $v1, (0b1001 << 12) | (2 << 16)
+	sw $v1, SET($v0)
 
 _refclk_wait:
 	lw $v1, 0($v0)
@@ -407,14 +414,6 @@
 	li $v1, 0b0001		/* ROSEL<3:0> = 0001 (PBCLK) */
 	sw $v1, SET($v0)
 
-	/*
-	The RODIV and ROTRIM values should be zero by default, yielding a
-	frequency of half the input indicated by ROSEL.
-	*/
-
-	li $v1, (1 << 9)	/* REFOCON<9> = DIVSWEN = 0 */
-	sw $v1, CLR($v0)
-
 	jr $ra
 	nop