# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1510059869 -3600
# Node ID aa1ac5755f03bf3efe9250987736d16821f43a8c
# Parent  9b3b13a6273395d9ae106267febd44eed67f813c
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled.

diff -r 9b3b13a62733 -r aa1ac5755f03 mips.h
--- a/mips.h	Fri Nov 03 23:25:06 2017 +0100
+++ b/mips.h	Tue Nov 07 14:04:29 2017 +0100
@@ -27,7 +27,10 @@
 
 #define STATUS_CP0	0x10000000
 #define STATUS_BEV	0x00400000
+
 #define STATUS_IRQ	0x0000fc00
+#define STATUS_IRQ_SHIFT	10
+
 #define STATUS_UM	0x00000010
 #define STATUS_ERL	0x00000004
 #define STATUS_EXL	0x00000002
diff -r 9b3b13a62733 -r aa1ac5755f03 vga.S
--- a/vga.S	Fri Nov 03 23:25:06 2017 +0100
+++ b/vga.S	Tue Nov 07 14:04:29 2017 +0100
@@ -284,8 +284,6 @@
 	la $v0, IPC2
 	li $v1, 0b11111
 	sw $v1, CLR($v0)	/* T2IP, T2IS = 0 */
-
-	la $v0, IPC2
 	li $v1, 0b11111
 	sw $v1, SET($v0)	/* T2IP = 7; T2IS = 3 */
 
@@ -628,6 +626,7 @@
 	mfc0 $t3, CP0_STATUS
 	li $t4, ~STATUS_IRQ	/* Clear interrupt priority bits. */
 	and $t3, $t3, $t4
+	ori $t3, $t3, (3 << STATUS_IRQ_SHIFT)
 	li $t4, ~STATUS_BEV	/* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
 	and $t3, $t3, $t4
 	ori $t3, $t3, STATUS_IE
@@ -890,12 +889,25 @@
 	li $v1, (1 << 4)	/* DCH0ECON<4> = SIRQEN = 1 */
 	sw $v1, SET($v0)
 
-	/* Disable the timer interrupt during the visible period. */
+	/*
+	Suspend delivery of the timer interrupt during the visible period.
+	The condition still occurs, however.
+	*/
 
 	la $v0, IEC0
 	li $v1, (1 << 9)
 	sw $v1, CLR($v0)	/* T2IE = 0 */
 
+	la $v0, IPC2
+	li $v1, 0b11111
+	sw $v1, CLR($v0)	/* T2IP, T2IS = 0 */
+	li $v1, 0b00111
+	sw $v1, SET($v0)	/* T2IP = 1; T2IS = 3 */
+
+	la $v0, IEC0
+	li $v1, (1 << 9)
+	sw $v1, SET($v0)	/* T2IE = 0 */
+
 _vbp_active_ret:
 	jr $ra
 	nop
@@ -915,7 +927,17 @@
 
 	la $s1, vfp_active
 
-	/* Re-enable the timer interrupt after the visible period. */
+	/* Restore delivery of the timer interrupt after the visible period. */
+
+	la $v0, IEC0
+	li $v1, (1 << 9)
+	sw $v1, CLR($v0)	/* T2IE = 0 */
+
+	la $v0, IPC2
+	li $v1, 0b11111
+	sw $v1, CLR($v0)	/* T2IP, T2IS = 0 */
+	li $v1, 0b11111
+	sw $v1, SET($v0)	/* T2IP = 7; T2IS = 3 */
 
 	la $v0, IEC0
 	li $v1, (1 << 9)