# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509828468 -3600
# Node ID ae02a1821af37580a8c176f1b1a706158e35573a
# Parent  5d02b5c6d920767172ddbc54c075d7d891f68da6
Make DMA channel 1 the line channel. Things will only now work if the Timer2
interrupt is not disabled, for some reason.

diff -r 5d02b5c6d920 -r ae02a1821af3 vga.S
--- a/vga.S	Sat Nov 04 21:33:58 2017 +0100
+++ b/vga.S	Sat Nov 04 21:47:48 2017 +0100
@@ -445,8 +445,8 @@
 	sw $v1, SET($v0)
 
 	/*
-	Initialise a line channel.
-	The line channel will be channel 0 (x = 0).
+	Initialise a start channel.
+	The start channel will be channel 0 (x = 0).
 
 	Specify a priority of 3:
 	DCHxCON<1:0> = CHPRI<1:0> = 3
@@ -460,8 +460,9 @@
 	sw $v1, 0($v0)
 
 	/*
-	Initialise a level reset channel.
-	The reset channel will be channel 1 (x = 1).
+	Initialise line and level reset channels.
+	The line channel will be channel 1 (x = 1).
+	The reset channel will be channel 2 (x = 2).
 
 	Specify a priority of 3:
 	DCHxCON<1:0> = CHPRI<1:0> = 3
@@ -495,8 +496,9 @@
 	sw $v1, 0($v0)
 
 	/*
-	Initiate reset channel transfer when channel 0 is finished:
-	DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt
+	Initiate line channel transfer when channel 0 is finished:
+	Initiate reset channel transfer when channel 1 is finished:
+	DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 or 1 interrupt
 	DCHxECON<4> = SIRQEN = 1
 	*/
 
@@ -513,17 +515,18 @@
 	DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
 	*/
 
-	la $v0, DCH0CSIZ
+	la $v0, DCH1CSIZ
 	li $v1, LINE_LENGTH
 	sw $v1, 0($v0)
 
 	/*
-	The reset channel has a cell size of a single zero byte:
+	The start and reset channels have a cell size of a single zero byte:
 	DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1
 	*/
 
-	la $v0, DCH1CSIZ
 	li $v1, 1
+
+	la $v0, DCH0CSIZ
 	sw $v1, 0($v0)
 
 	la $v0, DCH2CSIZ
@@ -534,12 +537,13 @@
 	DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
 	*/
 
-	la $v0, DCH0SSIZ
+	la $v0, DCH1SSIZ
 	li $v1, LINE_LENGTH
 	sw $v1, 0($v0)
 
-	la $v0, DCH1SSIZ
 	li $v1, 1
+
+	la $v0, DCH0SSIZ
 	sw $v1, 0($v0)
 
 	la $v0, DCH2SSIZ
@@ -550,25 +554,23 @@
 	DCHxSSA = physical(line data address)
 	*/
 
-	la $v0, DCH0SSA
+	la $v0, DCH1SSA
 	li $v1, SCREEN_BASE
 	sw $v1, 0($v0)
 
 	/*
-	For the reset channel, a single byte of zero is transferred:
+	For the start and reset channels, a single byte of zero is transferred:
 	DCHxSSA = physical(zero data address)
 	*/
 
-	la $v0, DCH1SSA
-	la $v1, fulldata
+	la $v1, zerodata
 	li $t8, KSEG0_BASE
 	subu $v1, $v1, $t8
+
+	la $v0, DCH0SSA
 	sw $v1, 0($v0)
 
 	la $v0, DCH2SSA
-	la $v1, zerodata
-	li $t8, KSEG0_BASE
-	subu $v1, $v1, $t8
 	sw $v1, 0($v0)
 
 	/*
@@ -576,8 +578,9 @@
 	DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1
 	*/
 
+	li $v1, 1
+
 	la $v0, DCH0DSIZ
-	li $v1, 1
 	sw $v1, 0($v0)
 
 	la $v0, DCH1DSIZ
@@ -591,10 +594,11 @@
 	DCHxDSA = physical(PORTB)
 	*/
 
-	la $v0, DCH0DSA
 	li $v1, PORTB
 	li $t8, KSEG1_BASE
 	subu $v1, $v1, $t8
+
+	la $v0, DCH0DSA
 	sw $v1, 0($v0)
 
 	la $v0, DCH1DSA
@@ -630,7 +634,7 @@
 	li $v1, (0b11 << 28)	/* IEC1<29:28> = DMA1IE, DMA0IE = 1 */
 	sw $v1, SET($v0)
 
-	/* Enable line channel. */
+	/* Enable start channel. */
 
 	la $v0, DCH0CON
 	li $v1, 0b10000000
@@ -642,9 +646,6 @@
 zerodata:
 .word 0
 
-fulldata:
-.word 255
-
 
 
 /* Utilities. */
@@ -927,21 +928,15 @@
 
 	/* Update the source address. */
 
-	la $v0, DCH0SSA
+	la $v0, DCH1SSA
 	sw $s2, 0($v0)
 
-	/* Enable the line channel for timer event transfer initiation. */
+	/* Enable the start channel for timer event transfer initiation. */
 
 	la $v0, DCH0ECON
 	li $v1, (1 << 4)	/* DCH0ECON<4> = SIRQEN = 1 */
 	sw $v1, SET($v0)
 
-	/* Disable the timer interrupt during the visible period. */
-
-	la $v0, IEC0
-	li $v1, (1 << 9)
-	sw $v1, CLR($v0)	/* T2IE = 0 */
-
 _vbp_active_ret:
 	jr $ra
 	nop
@@ -961,12 +956,6 @@
 
 	la $s1, vfp_active
 
-	/* Re-enable the timer interrupt after the visible period. */
-
-	la $v0, IEC0
-	li $v1, (1 << 9)
-	sw $v1, SET($v0)	/* T2IE = 1 */
-
 _visible_active_ret:
 	jr $ra
 	nop
@@ -983,7 +972,7 @@
 	bne $s1, $v0, _visible_update_address
 	nop
 
-	/* Disable the line channel. */
+	/* Disable the start channel. */
 
 	la $v0, DCH0ECON
 	li $v1, (1 << 4)	/* DCH0ECON<4> = SIRQEN = 0 */
@@ -1022,7 +1011,7 @@
 
 	/* Update the source address. */
 
-	la $v0, DCH0SSA
+	la $v0, DCH1SSA
 	sw $s2, 0($v0)
 
 _visible_update_ret: