# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509666016 -3600
# Node ID c5b54afa496d73271c99f9de5d21bf12ac7a8a83
# Parent  70fc39a067073463413eca7de481a871c9193009
Fixed comments.

diff -r 70fc39a06707 -r c5b54afa496d vga.S
--- a/vga.S	Fri Sep 29 22:10:11 2017 +0200
+++ b/vga.S	Fri Nov 03 00:40:16 2017 +0100
@@ -262,7 +262,7 @@
 
 init_timer2:
 
-	/* Initialise Timer2 interrupt. */
+	/* Initialise Timer2 for sync pulses. */
 
 	la $v0, T2CON
 	sw $zero, 0($v0)	/* T2CON = 0 */
@@ -312,7 +312,7 @@
 data has been transferred using DMA, but this is achieved by just choosing
 suitable start and end values.
 
-Using OC2, Timer 2 triggers a level shifting event and OC2 is reconfigured to
+Using OC2, Timer2 triggers a level shifting event and OC2 is reconfigured to
 reverse the level at a later point. In this way, the vsync pulse is generated
 and is synchronised to the display lines.
 */
@@ -511,7 +511,7 @@
 
 	/*
 	The reset channel has a cell size of a single zero byte:
-	DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
+	DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1
 	*/
 
 	la $v0, DCH1CSIZ
@@ -520,7 +520,7 @@
 
 	/*
 	The source has a size identical to the cell size:
-	DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH
+	DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
 	*/
 
 	la $v0, DCH0SSIZ