# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1509811635 -3600
# Node ID d782a0c62e19523c34afb06b18bd541dcaa3113e
# Parent  9b3b13a6273395d9ae106267febd44eed67f813c
Experiment with the use of CLKO providing the clock pulse of a flip-flop
attempting to buffer the output.

diff -r 9b3b13a62733 -r d782a0c62e19 README.txt
--- a/README.txt	Fri Nov 03 23:25:06 2017 +0100
+++ b/README.txt	Sat Nov 04 17:07:15 2017 +0100
@@ -39,7 +39,7 @@
        D3/RB3  7      22 RB11/PGEC2
                8      21 RB10/PGEC3
           RA2  9      20
-          RA3 10      19
+     CLKO/RA3 10      19
        D4/RB4 11      18 RB9
               12      17 RB8
               13      16 RB7/D7
@@ -47,6 +47,26 @@
 
 Note that RB6 is not available on pin 15 on this device.
 
+Clock Output Routing
+--------------------
+
+CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
+data signals then routed through the flip-flop as follows:
+
+          MR#  1  \/  20 VCC
+    out D0/Q0  2      19 Q7/D7 out
+     in D0/D0  3      18 D7/D7 in
+     in D1/D1  4      17 D6
+    out D1/Q1  5      16 Q6
+    out D2/Q2  6      15 Q5/D5 out
+     in D2/D2  7      14 D5/D5 in
+     in D3/D3  8      13 D4/D4 in
+    out D3/Q3  9      12 Q4/D4 out
+          GND 10      11 CP/CLKO in
+
+MR# is kept at a high level. All out signals are then supplied to the
+analogue circuit provided below.
+
 Data Signal Routing
 -------------------
 
diff -r 9b3b13a62733 -r d782a0c62e19 vga.S
--- a/vga.S	Fri Nov 03 23:25:06 2017 +0100
+++ b/vga.S	Sat Nov 04 17:07:15 2017 +0100
@@ -32,12 +32,16 @@
 
 The watchdog timer (FWDTEN) is also disabled.
 
+The primary oscillator is configured to provide an external clock and CLKO
+output is enabled.
+
 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
 RPB4.
 */
 
 .section .devcfg1, "a"
-.word 0xff7fdfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
+.word 0xff7fd8d9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
+			DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
 			DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
 
 /*
@@ -115,7 +119,7 @@
 	li $t1, (1 << 3)	/* PORTA<3> = RA3 */
 	sw $t1, CLR($t0)
 
-	jal init_oc_pins
+	jal init_io_pins
 	nop
 
 	/* Initialise the status register. */
@@ -376,7 +380,9 @@
 	jr $ra
 	nop
 
-init_oc_pins:
+
+
+init_io_pins:
 	/* Unlock the configuration register bits. */
 
 	la $v0, SYSKEY
@@ -403,6 +409,14 @@
 	li $v1, 0b0101		/* RPA1R<3:0> = 0101 (OC2) */
 	sw $v1, 0($v0)
 
+	/* Map REFCLKO to RPA2. */
+
+	la $v0, RPA2R
+	li $v1, 0b0111		/* RPA2R<3:0> = 0111 (REFCLKO) */
+	sw $v1, 0($v0)
+
+	/* Restore CFGCON. */
+
 	la $v0, CFGCON
 	sw $t8, 0($v0)