# HG changeset patch # User Paul Boddie # Date 1509737465 -3600 # Node ID db8794469a716890d89915a7c0c536902159a2f9 # Parent eebebd2d4062cb848097085423179e805946ff37 Change the DMA channels used from 0 and 1 to 1 and 2. diff -r eebebd2d4062 -r db8794469a71 vga.S --- a/vga.S Fri Nov 03 01:20:19 2017 +0100 +++ b/vga.S Fri Nov 03 20:31:05 2017 +0100 @@ -429,13 +429,13 @@ /* Disable DMA interrupts. */ la $v0, IEC1 - li $v1, (3 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 0 */ + li $v1, (0b111 << 28) /* IEC1<30:28> = DMA2IE, DMA1IE, DMA0IE = 0 */ sw $v1, CLR($v0) /* Clear DMA interrupt flags. */ la $v0, IFS1 - li $v1, (3 << 28) /* IFS1<29:28> = DMA1IF, DMA0IF = 0 */ + li $v1, (0b111 << 28) /* IFS1<30:28> = DMA2IF, DMA1IF, DMA0IF = 0 */ sw $v1, CLR($v0) /* Enable DMA. */ @@ -446,7 +446,7 @@ /* Initialise a line channel. - The line channel will be channel 0 (x = 0). + The line channel will be channel 1 (x = 1). Specify a priority of 3: DCHxCON<1:0> = CHPRI<1:0> = 3 @@ -455,13 +455,13 @@ DCHxCON<4> = CHAEN = 1 */ - la $v0, DCH0CON + la $v0, DCH1CON li $v1, 0b10011 sw $v1, 0($v0) /* Initialise a level reset channel. - The reset channel will be channel 1 (x = 1). + The reset channel will be channel 2 (x = 2). Specify a priority of 3: DCHxCON<1:0> = CHPRI<1:0> = 3 @@ -473,7 +473,7 @@ DCHxCON<6> = CHAED = 1 */ - la $v0, DCH1CON + la $v0, DCH2CON li $v1, 0b1100011 sw $v1, 0($v0) @@ -486,18 +486,18 @@ For now, however, prevent initiation by not setting SIRQEN. */ - la $v0, DCH0ECON + la $v0, DCH1ECON li $v1, (9 << 8) sw $v1, 0($v0) /* - Initiate reset channel transfer when channel 0 is finished: - DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt + Initiate reset channel transfer when channel 1 is finished: + DCHxECON<15:8> = CHSIRQ<7:0> = channel 1 interrupt DCHxECON<4> = SIRQEN = 1 */ - la $v0, DCH1ECON - li $v1, (60 << 8) | (1 << 4) + la $v0, DCH2ECON + li $v1, (61 << 8) | (1 << 4) sw $v1, 0($v0) /* @@ -505,7 +505,7 @@ DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH */ - la $v0, DCH0CSIZ + la $v0, DCH1CSIZ li $v1, LINE_LENGTH sw $v1, 0($v0) @@ -514,7 +514,7 @@ DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1 */ - la $v0, DCH1CSIZ + la $v0, DCH2CSIZ li $v1, 1 sw $v1, 0($v0) @@ -523,11 +523,11 @@ DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1 */ - la $v0, DCH0SSIZ + la $v0, DCH1SSIZ li $v1, LINE_LENGTH sw $v1, 0($v0) - la $v0, DCH1SSIZ + la $v0, DCH2SSIZ li $v1, 1 sw $v1, 0($v0) @@ -536,7 +536,7 @@ DCHxSSA = physical(line data address) */ - la $v0, DCH0SSA + la $v0, DCH1SSA li $v1, SCREEN_BASE sw $v1, 0($v0) @@ -545,7 +545,7 @@ DCHxSSA = physical(zero data address) */ - la $v0, DCH1SSA + la $v0, DCH2SSA la $v1, zerodata li $t8, KSEG0_BASE subu $v1, $v1, $t8 @@ -556,11 +556,11 @@ DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1 */ - la $v0, DCH0DSIZ + la $v0, DCH1DSIZ li $v1, 1 sw $v1, 0($v0) - la $v0, DCH1DSIZ + la $v0, DCH2DSIZ sw $v1, 0($v0) /* @@ -568,13 +568,13 @@ DCHxDSA = physical(PORTB) */ - la $v0, DCH0DSA + la $v0, DCH1DSA li $v1, PORTB li $t8, KSEG1_BASE subu $v1, $v1, $t8 sw $v1, 0($v0) - la $v0, DCH1DSA + la $v0, DCH2DSA sw $v1, 0($v0) /* @@ -582,27 +582,27 @@ address can be updated. */ - la $v0, DCH0INT + la $v0, DCH1INT li $v1, (1 << 19) /* CHBCIE = 1 */ sw $v1, 0($v0) /* Enable interrupt for address updating. */ la $v0, IPC10 - li $v1, 0b11111 /* DMA0IP, DMA0IS = 0 */ + li $v1, 0b1111100000000 /* DMA1IP, DMA1IS = 0 */ sw $v1, CLR($v0) la $v0, IPC10 - li $v1, 0b11111 /* DMA0IP = 7, DMA0IS = 3 */ + li $v1, 0b1111100000000 /* DMA1IP = 7, DMA1IS = 3 */ sw $v1, SET($v0) la $v0, IEC1 - li $v1, (1 << 28) /* IEC1<28> = DMA0IE = 1 */ + li $v1, (1 << 29) /* IEC1<29> = DMA1IE = 1 */ sw $v1, SET($v0) /* Enable line channel. */ - la $v0, DCH0CON + la $v0, DCH1CON li $v1, 0b10000000 sw $v1, SET($v0) @@ -752,19 +752,19 @@ la $v0, IFS1 lw $v1, 0($v0) - li $t8, (1 << 28) /* DMA0IF */ + li $t8, (1 << 29) /* DMA1IF */ and $v1, $v1, $t8 beqz $v1, irq_exit nop /* Clear the DMA interrupt condition. */ - li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */ + li $v1, (1 << 29) /* IFS1<29> = DMA1IF = 0 */ sw $v1, CLR($v0) /* Test the block transfer completion interrupt flag. */ - la $v0, DCH0INT + la $v0, DCH1INT lw $v1, 0($v0) andi $v1, $v1, (1 << 3) /* CHBCIF */ beqz $v1, irq_exit @@ -884,13 +884,13 @@ /* Update the source address. */ - la $v0, DCH0SSA + la $v0, DCH1SSA sw $s2, 0($v0) /* Enable the line channel for timer event transfer initiation. */ - la $v0, DCH0ECON - li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */ + la $v0, DCH1ECON + li $v1, (1 << 4) /* DCH1ECON<4> = SIRQEN = 1 */ sw $v1, SET($v0) /* Disable the timer interrupt during the visible period. */ @@ -948,8 +948,8 @@ /* Disable the line channel. */ - la $v0, DCH0ECON - li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */ + la $v0, DCH1ECON + li $v1, (1 << 4) /* DCH1ECON<4> = SIRQEN = 0 */ sw $v1, CLR($v0) j _visible_update_ret @@ -985,18 +985,18 @@ /* Disable line channel. */ - la $v0, DCH0CON + la $v0, DCH1CON li $v1, 0b10000000 sw $v1, CLR($v0) /* Update the source address. */ - la $v0, DCH0SSA + la $v0, DCH1SSA sw $s2, 0($v0) /* Enable line channel. */ - la $v0, DCH0CON + la $v0, DCH1CON sw $v1, SET($v0) _visible_update_ret: