1.1 --- a/vga.S Mon Nov 06 19:12:01 2017 +0100
1.2 +++ b/vga.S Mon Nov 06 19:12:47 2017 +0100
1.3 @@ -28,7 +28,7 @@
1.4
1.5 /*
1.6 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.7 -divided by 2, and FRCDIV+PLL selected.
1.8 +divided by 1, and FRCDIV+PLL selected.
1.9
1.10 The watchdog timer (FWDTEN) is also disabled.
1.11
1.12 @@ -37,7 +37,7 @@
1.13 */
1.14
1.15 .section .devcfg1, "a"
1.16 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.17 +.word 0xff7fcfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 0;
1.18 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.19
1.20 /*
2.1 --- a/vga.h Mon Nov 06 19:12:01 2017 +0100
2.2 +++ b/vga.h Mon Nov 06 19:12:47 2017 +0100
2.3 @@ -4,9 +4,9 @@
2.4 #define LINE_LENGTH 160 /* pixels */
2.5 #define LINE_COUNT 256 /* distinct display lines */
2.6
2.7 -#define HFREQ_LIMIT 643 /* 24MHz cycles */
2.8 -#define HSYNC_START 460 /* 24MHz cycles */
2.9 -#define HSYNC_LIMIT 64 /* 24MHz cycles */
2.10 +#define HFREQ_LIMIT 1286 /* 48MHz cycles */
2.11 +#define HSYNC_START 920 /* 48MHz cycles */
2.12 +#define HSYNC_LIMIT 128 /* 48MHz cycles */
2.13 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
2.14
2.15 #define VISIBLE_START 70 /* horizontal lines, back porch end */